Datasheet LTC2391-16 (Analog Devices) - 5
| Fabricante | Analog Devices |
| Descripción | 16-Bit, 250ksps SAR ADC with 94dB SNR |
| Páginas / Página | 24 / 5 — TIMING CHARACTERISTICS. The. denotes the specifi cations which apply over … |
| Formato / tamaño de archivo | PDF / 229 Kb |
| Idioma del documento | Inglés |
TIMING CHARACTERISTICS. The. denotes the specifi cations which apply over the full operating temperature
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LTC2391-16
TIMING CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Sampling Frequency l 250 ksps tCONV Conversion Time l 2500 ns tACQ Acquisition Time l 1485 ns t4 CNVST Low Time l 20 ns t5 CNVST High Time l 250 ns t6 CNVST↓ to BUSY Delay CL = 15pF l 15 ns t7 RESET Pulse Width l 5 ns t8 SCLK Period (Note 9) l 12.5 ns t9 SCLK High Time l 4 ns t10 SCLK Low Time l 4 ns tr , tf SCLK Rise and Fall Times (Note 10) 1 μs t11 SDIN Setup Time l 2 ns t12 SDIN Hold Time l 1 ns t13 SDOUT Delay After SCLK↑ CL = 15pF l 2 8 ns t14 SDOUT Delay After CS↓ l 8 ns t15 CS↓ to SCLK Setup Time l 20 ns t16 Data Valid to BUSY↓ l 1 ns t17 Data Access Time after RD↓ or BYTESWAP↑ l 10 ns t18 Bus Relinquish Time l 10 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 7:
Bipolar zero error is the offset voltage measured from –0.5LSB may cause permanent damage to the device. Exposure to any Absolute when the output code fl ickers between 0000 0000 0000 0000 and 1111 Maximum Rating condition for extended periods may affect device 1111 1111 1111. Bipolar full-scale error is the worst-case of –FS or +FS reliability and lifetime. untrimmed deviation from ideal fi rst and last code transitions and includes
Note 2:
All voltage values are with respect to ground. the effect of offset error.
Note 3:
When these pin voltages are taken below ground or above
Note 8:
All specifi cations in dB are referred to a full-scale ±4.096V input AVP, DVP or OVP, they will be clamped by internal diodes. This product can with a 4.096V reference voltage. handle input currents up to 100mA below ground or above AVP, DVP or
Note 9:
t13 of 8ns maximum allows a shift clock frequency up to OVP without latchup. 2 • (t13 + tSETUP) for falling edge capture with 50% duty cycle and up to
Note 4:
AVP = DVP = OVP = 5V, f 80MHz for rising capture. t SMPL = 250ksps, external reference equal SETUP is the set-up time of the receiving logic. to 4.096V unless otherwise noted.
Note 10:
Guaranteed by design.
Note 5:
Recommended operating conditions.
Note 11:
Temperature coeffi cient is calculated by dividing the maximum
Note 6:
Integral nonlinearity is defi ned as the deviation of a code from a change in output voltage by the specifi ed temperature range. straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. 4V tWIDTH 0.5V t t 50% 50% DELAY DELAY 239116F01 4V 4V 0.5V 0.5V
Figure 1. Voltage Levels for Timing Specifi cations
239116fa 5
TIMING CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Sampling Frequency l 250 ksps tCONV Conversion Time l 2500 ns tACQ Acquisition Time l 1485 ns t4 CNVST Low Time l 20 ns t5 CNVST High Time l 250 ns t6 CNVST↓ to BUSY Delay CL = 15pF l 15 ns t7 RESET Pulse Width l 5 ns t8 SCLK Period (Note 9) l 12.5 ns t9 SCLK High Time l 4 ns t10 SCLK Low Time l 4 ns tr , tf SCLK Rise and Fall Times (Note 10) 1 μs t11 SDIN Setup Time l 2 ns t12 SDIN Hold Time l 1 ns t13 SDOUT Delay After SCLK↑ CL = 15pF l 2 8 ns t14 SDOUT Delay After CS↓ l 8 ns t15 CS↓ to SCLK Setup Time l 20 ns t16 Data Valid to BUSY↓ l 1 ns t17 Data Access Time after RD↓ or BYTESWAP↑ l 10 ns t18 Bus Relinquish Time l 10 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 7:
Bipolar zero error is the offset voltage measured from –0.5LSB may cause permanent damage to the device. Exposure to any Absolute when the output code fl ickers between 0000 0000 0000 0000 and 1111 Maximum Rating condition for extended periods may affect device 1111 1111 1111. Bipolar full-scale error is the worst-case of –FS or +FS reliability and lifetime. untrimmed deviation from ideal fi rst and last code transitions and includes
Note 2:
All voltage values are with respect to ground. the effect of offset error.
Note 3:
When these pin voltages are taken below ground or above
Note 8:
All specifi cations in dB are referred to a full-scale ±4.096V input AVP, DVP or OVP, they will be clamped by internal diodes. This product can with a 4.096V reference voltage. handle input currents up to 100mA below ground or above AVP, DVP or
Note 9:
t13 of 8ns maximum allows a shift clock frequency up to OVP without latchup. 2 • (t13 + tSETUP) for falling edge capture with 50% duty cycle and up to
Note 4:
AVP = DVP = OVP = 5V, f 80MHz for rising capture. t SMPL = 250ksps, external reference equal SETUP is the set-up time of the receiving logic. to 4.096V unless otherwise noted.
Note 10:
Guaranteed by design.
Note 5:
Recommended operating conditions.
Note 11:
Temperature coeffi cient is calculated by dividing the maximum
Note 6:
Integral nonlinearity is defi ned as the deviation of a code from a change in output voltage by the specifi ed temperature range. straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. 4V tWIDTH 0.5V t t 50% 50% DELAY DELAY 239116F01 4V 4V 0.5V 0.5V
Figure 1. Voltage Levels for Timing Specifi cations
239116fa 5