Datasheet LTC2389-18 (Analog Devices) - 5

FabricanteAnalog Devices
Descripción18-Bit, 2.5Msps SAR ADC with Pin-Configurable Analog Input Range and 99.8dB SNR
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Digi. Tal inpuTs anD DigiTal ouTpuTs The. denotes the specifications which apply over the full

Digi Tal inpuTs anD DigiTal ouTpuTs The denotes the specifications which apply over the full

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LTC2389-18
Digi Tal inpuTs anD DigiTal ouTpuTs The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage l 0.8 • OVDD V VIL Low Level Input Voltage l 0.2 • OVDD V IIN Digital Input Current VIN = 0V to OVDD l –10 10 µA CIN Digital Input Capacitance 5 pF VOH High Level Output Voltage IOUT = –500µA l OVDD – 0.2 V VOL Low Level Output Voltage IOUT = 500µA l 0.2 V IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l –10 10 µA ISOURCE Output Source Current VOUT = 0V –10 mA ISINK Output Sink Current VOUT = OVDD 10 mA
p ower requiremenTs The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage l 4.75 5 5.25 V OVDD Supply Voltage l 1.71 5.25 V IVDD Core Supply Current 2.5Msps Sample Rate l 32.5 36 mA 2.5Msps Sample Rate, Internal Reference Enabled 34.1 mA IOVDD I/O Supply Current 2.5Msps Sample Rate (CL = 15pF) 1.6 mA IPD Power Down Current Conversion Done, PD = OVDD, Other Digital Inputs l 15 250 µA (IVDD + IOVDD) Tied to OVDD or GND PD Power Dissipation 2.5Msps Sample Rate 162.5 180 mW Conversion Done, PD = OVDD, Other Digital Inputs 75 1250 µW Tied to OVDD or GND
Timing characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Sampling Frequency Parallel Output Modes l 2.5 Msps Serial Output Mode l 1.9 Msps tCONV Conversion Time l 245 280 310 ns tACQ Acquisition Time tACQ = tCYC – tCONV – tBUSYLH (Note 10) l 77 110 ns tCYC Time Between CNVST↓ l 400 ns tCNVSTL CNVST Low Time l 20 ns tCNVSTH CNVST High Time l 200 ns tBUSYLH CNVST↓ to BUSY Delay CL = 15pF l 13 ns tRESETH RESET Pulse Width l 200 ns tSCK SCK Period (Notes 5, 11) l 10 ns tSCKH SCK High Time l 4 ns tSCKL SCK Low Time l 4 ns tDSCK SCK↓ Delay From CS↓ l 10 ns tSSDI SDI Setup Time From SCK↓ l 2 ns 238918f 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Analog Input Converter Characteristics Dynamic Accuracy Reference Characteristics Digital Inputs And Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagrams Applications Information Package Description Typical Application Related Parts