Datasheet LTC2386-18 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | 18-Bit, 10Msps SAR ADC |
| Páginas / Página | 22 / 9 — pin FuncTions DCO–/DCO+ (Pins 19/20):. OVDD (Pin 22):. VDDL (Pins 30, … |
| Formato / tamaño de archivo | PDF / 1.2 Mb |
| Idioma del documento | Inglés |
pin FuncTions DCO–/DCO+ (Pins 19/20):. OVDD (Pin 22):. VDDL (Pins 30, 31):. CLK–/CLK+ (Pins 23/24):. VCM (Pin 32):
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LTC2386-18
pin FuncTions DCO–/DCO+ (Pins 19/20):
LVDS Data Clock Output. This into the hold mode and starts a conversion cycle. CNV+ is an echoed version of CLK–/CLK+ that can be used to can also be driven with a 2.5V CMOS signal if CNV– is latch the data outputs. tied to GND.
OVDD (Pin 22):
2.5V Output Power Supply. The range of
VDDL (Pins 30, 31):
2.5V Analog Power Supply. The OVDD is 2.375V to 2.625V. Bypass to GND with a 0.1μF range of VDDL is 2.375V to 2.625V. The two pins should ceramic capacitor. be shorted together and bypassed to GND with 0.1μF and
CLK–/CLK+ (Pins 23/24):
LVDS Clock Input. This is an 10μF ceramic capacitors. externally applied clock that serially shifts out the conver-
VCM (Pin 32):
Common Mode Output. VCM, nominally sion result. 2.048V, can be used to set the common mode of the ana-
TWOLANES (Pin 25):
Digital input that enables two-lane log inputs. Bypass to GND with a 0.1μF ceramic capacitor output mode. When TWOLANES is high (two-lane output close to the pin. If VCM is not used, the bypass capacitor mode), the ADC outputs two bits at a time on DA–/DA+ is not necessary as long as the parasitic capacitance on and DB–/DB+. When TWOLANES is low (one-lane output the VCM pin is under 10pF. mode), the ADC outputs one bit at a time on DA–/DA+, and
Exposed Pad (Pin 33):
The exposed pad on the bottom DB–/DB+ are disabled. Logic levels are determined by VDDL. of the package. Connect to the ground plane of the PCB
CNV–/CNV+ (Pins 27/28):
Conversion Start LVDS Input. using multiple vias. A rising edge on CNV+ puts the internal sample-and-hold
FuncTional block DiagraM
VDD VDDL OVDD CNV TWOLANES CONTROL LOGIC TESTPAT PD CLK IN+ + DCO SERIAL 18-BIT, 10Msps ADC LVDS DA IN– INTERFACE – DB VCM 0.5 15k 2 2.048V REFERENCE GND REFGND REFBUF REFIN 238618 BD 238618f For more information www.linear.com/LTC2386-18 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Typical Application Related Parts
pin FuncTions DCO–/DCO+ (Pins 19/20):
LVDS Data Clock Output. This into the hold mode and starts a conversion cycle. CNV+ is an echoed version of CLK–/CLK+ that can be used to can also be driven with a 2.5V CMOS signal if CNV– is latch the data outputs. tied to GND.
OVDD (Pin 22):
2.5V Output Power Supply. The range of
VDDL (Pins 30, 31):
2.5V Analog Power Supply. The OVDD is 2.375V to 2.625V. Bypass to GND with a 0.1μF range of VDDL is 2.375V to 2.625V. The two pins should ceramic capacitor. be shorted together and bypassed to GND with 0.1μF and
CLK–/CLK+ (Pins 23/24):
LVDS Clock Input. This is an 10μF ceramic capacitors. externally applied clock that serially shifts out the conver-
VCM (Pin 32):
Common Mode Output. VCM, nominally sion result. 2.048V, can be used to set the common mode of the ana-
TWOLANES (Pin 25):
Digital input that enables two-lane log inputs. Bypass to GND with a 0.1μF ceramic capacitor output mode. When TWOLANES is high (two-lane output close to the pin. If VCM is not used, the bypass capacitor mode), the ADC outputs two bits at a time on DA–/DA+ is not necessary as long as the parasitic capacitance on and DB–/DB+. When TWOLANES is low (one-lane output the VCM pin is under 10pF. mode), the ADC outputs one bit at a time on DA–/DA+, and
Exposed Pad (Pin 33):
The exposed pad on the bottom DB–/DB+ are disabled. Logic levels are determined by VDDL. of the package. Connect to the ground plane of the PCB
CNV–/CNV+ (Pins 27/28):
Conversion Start LVDS Input. using multiple vias. A rising edge on CNV+ puts the internal sample-and-hold
FuncTional block DiagraM
VDD VDDL OVDD CNV TWOLANES CONTROL LOGIC TESTPAT PD CLK IN+ + DCO SERIAL 18-BIT, 10Msps ADC LVDS DA IN– INTERFACE – DB VCM 0.5 15k 2 2.048V REFERENCE GND REFGND REFBUF REFIN 238618 BD 238618f For more information www.linear.com/LTC2386-18 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Typical Application Related Parts