Datasheet LTC2380-24 (Analog Devices) - 9

LTC2380-24
PIN FUNCTIONS CHAIN (Pin 1):
Chain Mode Selector Pin. When low, the
BUSY (Pin 11):
BUSY Indicator. Goes high at the start of LTC2380-24 operates in normal mode and the RDL/SDI a new conversion and returns low when the conversion input pin functions to enable or disable SDO. When high, has finished. Logic levels are determined by OVDD. the LTC2380-24 operates in chain mode and the RDL/SDI
RDL/SDI (Pin 12):
Bus Enabling Input/Serial Data Input pin functions as SDI, the daisy-chain serial data input. Pin. This pin serves two functions depending on whether Logic levels are determined by OVDD. the part is operating in normal mode (CHAIN pin low) or
VDD (Pin 2):
2.5V Power Supply. The range of VDD is chain mode(CHAIN pin high). In normal mode, RDL/SDI 2.375V to 2.625V. Bypass VDD to GND with a 10µF ce- is a bus enabling input for the serial data I/O bus. When ramic capacitor. RDL/SDI is low in normal mode, data is read out of the
GND (Pins 3, 6, 10 and 16):
Ground. ADC on the SDO pin. When RDL/SDI is high in normal mode, SDO becomes Hi-Z and SCK is disabled. In chain
IN+, IN– (Pins 4, 5):
Positive and Negative Differential mode, RDL/SDI acts as a serial data input pin where data Analog Inputs. from another ADC in the daisy chain is input. Logic levels
REF (Pin 7):
Reference Input. The range of REF is 2.5V are determined by OVDD. to 5.1V. This pin is referred to the GND pin and should be
SCK (Pin 13):
Serial Data Clock Input. When SDO is enabled, decoupled closely to the pin with a 47µF ceramic capacitor the conversion result or daisy-chain data from another (X7R, 1210 size, 10V rating). ADC is shifted out on the rising edges of this clock MSB
REF/DGC (Pin 8):
When tied to REF, digital gain compres- first. Logic levels are determined by OVDD. sion is disabled and the LTC2380-24 defines full-scale ac-
SDO (Pin 14):
Serial Data Output. The conversion result or cording to the ±VREF analog input range. When tied to GND, daisy-chain data is output on this pin on each rising edge digital gain compression is enabled and the LTC2380-24 of SCK MSB first. The output data is in 2’s complement defines full-scale with inputs that swing between 10% and format. Logic levels are determined by OVDD. 90% of the ±VREF analog input range.
OVDD (Pin 15):
I/O Interface Digital Power. The range of
CNV (Pin 9):
Convert Input. A rising edge on this input OVDD is 1.71V to 5.25V. This supply is nominally set to powers up the part and initiates a new conversion. Logic the same supply as the host interface (1.8V, 2.5V, 3.3V, levels are determined by OVDD. or 5V). Bypass OVDD to GND with a 0.1µF capacitor.
GND (Exposed Pad Pin 17 – DFN Package Only):
Ground. Exposed pad must be soldered directly to the ground plane. 238024fa For more information www.linear.com/LTC2380-24 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Reference Input Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Revision History Typical Application Related Parts