Datasheet LTC2368-24 (Analog Devices) - 9

LTC2368-24
PIN FUNCTIONS CHAIN (Pin 1):
Chain Mode Selector Pin. When low, the
BUSY (Pin 11):
BUSY Indicator. Goes high at the start of LTC2368-24 operates in normal mode and the RDL/SDI a new conversion and returns low when the conversion input pin functions to enable or disable SDO. When high, has finished. Logic levels are determined by OVDD. the LTC2368-24 operates in chain mode and the RDL/SDI
RDL/SDI (Pin 12):
Bus Enabling Input/Serial Data Input pin functions as SDI, the daisy-chain serial data input. Pin. This pin serves two functions depending on whether Logic levels are determined by OVDD. the part is operating in normal mode (CHAIN pin low) or
VDD (Pin 2):
2.5V Power Supply. The range of VDD is chain mode(CHAIN pin high). In normal mode, RDL/SDI 2.375V to 2.625V. Bypass VDD to GND with a 10µF ce- is a bus enabling input for the serial data I/O bus. When ramic capacitor. RDL/SDI is low in normal mode, data is read out of the
GND (Pins 3, 6, 10 and 16):
Ground. ADC on the SDO pin. When RDL/SDI is high in normal mode, SDO becomes Hi-Z and SCK is disabled. In chain
IN+ (Pin 4):
Analog Input. IN+ operates differential with mode, RDL/SDI acts as a serial data input pin where data respect to IN– with an IN+ to IN– range of 0V to VREF. from another ADC in the daisy chain is input. Logic levels
IN– (Pin 5):
Analog Ground Sense. IN– has an input range are determined by OVDD. of ±100mV with respect to GND and must be tied to the
SCK (Pin 13):
Serial Data Clock Input. When SDO is enabled, ground plane or a remote ground sense. the conversion result or daisy-chain data from another
REF (Pins 7, 8):
Reference Input. The range of REF is 2.5V ADC is shifted out on the rising edges of this clock MSB to 5.1V. This pin is referred to the GND pin and should be first. Logic levels are determined by OVDD. decoupled closely to the pin with a 47µF ceramic capacitor
SDO (Pin 14):
Serial Data Output. The conversion result (X7R, 1210 size, 10V rating). or daisy-chain data is output on this pin on each rising
CNV (Pin 9):
Convert Input. A rising edge on this input edge of SCK MSB first. The output data is in straight binary powers up the part and initiates a new conversion. Logic format. Logic levels are determined by OVDD. levels are determined by OVDD.
OVDD (Pin 15):
I/O Interface Digital Power. The range of OVDD is 1.71V to 5.25V. This supply is nominally set to the same supply as the host interface (1.8V, 2.5V, 3.3V, or 5V). Bypass OVDD to GND with a 0.1µF capacitor.
GND (Exposed Pad Pin 17 – DFN Package Only):
Ground. Exposed pad must be soldered directly to the ground plane. 236824f For more information www.linear.com/LTC2368-24 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Reference Input Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Typical Application Related Parts