LTC2360/LTC2361/LTC2362 BLOCK DIAGRAM 2.2μF 2.2μF + + 1 5 VDD OVDD ANALOG AIN INPUT 4 RANGE THREE-STATE SDO 0V TO V SERIAL REF S AND H 12-BIT ADC 6 OUTPUT PORT VREF 2 SCK 7 2.2μF GND TIMING LOGIC CONV 3 8 TS8 PACKAGE 236012 BD TIMING DIAGRAMS t8 t7 CONV 1.6V SCK 1.6V Hi-Z SDO VIH 236012 F01 SDO VIL 236012 F02 Figure 1. SDO Into Hi-Z State After CONV Rising EdgeFigure 2. SDO Data Valid Hold Time After SCK Falling Edge t4 SCK 1.6V VIH SDO VIL 236012 F03 Figure 3. SDO Data Valid Acess Time After SCK Falling Edge 236012fa 10