Datasheet LTC2328-18 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | 18-Bit, 1Msps, ±10.24V True Bipolar, Pseudo-Differential Input ADC with 95dB SNR |
| Páginas / Página | 26 / 6 — elecTrical characTerisTics Note 1:. Note 7:. Note 2:. Note 3:. Note 8:. … |
| Formato / tamaño de archivo | PDF / 518 Kb |
| Idioma del documento | Inglés |
elecTrical characTerisTics Note 1:. Note 7:. Note 2:. Note 3:. Note 8:. Note 9:. Note 4:. Note 10:. Note 11:. Note 5:. Note 12:. Note 6:
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LTC2328-18
elecTrical characTerisTics Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 7:
Bipolar zero error is the offset voltage measured from –0.5LSB may cause permanent damage to the device. Exposure to any Absolute when the output code flickers between 00 0000 0000 0000 0000 and 11 Maximum Rating condition for extended periods may affect device 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS reliability and lifetime. or +FS untrimmed deviation from ideal first and last code transitions and
Note 2:
All voltage values are with respect to ground. includes the effect of offset error.
Note 3:
When these pin voltages are taken below ground or above V
Note 8:
All specifications in dB are referred to a full-scale ±10.24V input DD or OV with REFIN = 2.048V. DD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above VDD or OVDD without
Note 9:
When REFBUF is overdriven, the internal reference buffer must be latch-up. turned off by setting REFIN = 0V.
Note 4:
VDD = 5V, OVDD = 2.5V, ±10.24V Range, REFIN = 2.048V,
Note 10:
fSMPL = 1MHz, IREFBUF varies proportionally with sample rate. fSMPL = 1MHz.
Note 11:
Guaranteed by design, not subject to test.
Note 5:
Recommended operating conditions.
Note 12:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
Note 6:
Integral nonlinearity is defined as the deviation of a code from a and OVDD = 5.25V. straight line passing through the actual endpoints of the transfer curve.
Note 13:
tSCK of 10ns maximum allows a shift clock frequency up to The deviation is measured from the center of the quantization band. 100MHz for rising edge capture.
Note 14:
Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. 0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 232818 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
Figure 1. Voltage Levels for Timing Specifications
232818fb 6 For more information www.linear.com/LTC2328-18 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Revision History Typical Application Related Parts
elecTrical characTerisTics Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 7:
Bipolar zero error is the offset voltage measured from –0.5LSB may cause permanent damage to the device. Exposure to any Absolute when the output code flickers between 00 0000 0000 0000 0000 and 11 Maximum Rating condition for extended periods may affect device 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS reliability and lifetime. or +FS untrimmed deviation from ideal first and last code transitions and
Note 2:
All voltage values are with respect to ground. includes the effect of offset error.
Note 3:
When these pin voltages are taken below ground or above V
Note 8:
All specifications in dB are referred to a full-scale ±10.24V input DD or OV with REFIN = 2.048V. DD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above VDD or OVDD without
Note 9:
When REFBUF is overdriven, the internal reference buffer must be latch-up. turned off by setting REFIN = 0V.
Note 4:
VDD = 5V, OVDD = 2.5V, ±10.24V Range, REFIN = 2.048V,
Note 10:
fSMPL = 1MHz, IREFBUF varies proportionally with sample rate. fSMPL = 1MHz.
Note 11:
Guaranteed by design, not subject to test.
Note 5:
Recommended operating conditions.
Note 12:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
Note 6:
Integral nonlinearity is defined as the deviation of a code from a and OVDD = 5.25V. straight line passing through the actual endpoints of the transfer curve.
Note 13:
tSCK of 10ns maximum allows a shift clock frequency up to The deviation is measured from the center of the quantization band. 100MHz for rising edge capture.
Note 14:
Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. 0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 232818 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
Figure 1. Voltage Levels for Timing Specifications
232818fb 6 For more information www.linear.com/LTC2328-18 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Revision History Typical Application Related Parts