Datasheet LTC2324-14 (Analog Devices)

LTC2324-14 Quad, 14-Bit + Sign, 2Msps/Ch Simultaneous Sampling ADC
FeaTures DescripTion
n
2Msps/Ch Throughput Rate
The LTC®2324-14 is a low noise, high speed quad n
Four Simultaneously Sampling Channels
14-bit + sign successive approximation register (SAR) n
Guaranteed 14-Bit, No Missing Codes
ADC with differential inputs and wide input common mode n
8VP-P Differential Inputs with Wide Input
range. Operating from a single 3.3V or 5V supply, the
Common Mode Range
LTC2324-14 has an 8VP-P differential input range, making n
81dB SNR (Typ) at fIN = 500kHz
it ideal for applications which require a wide dynamic n
–90dB THD (Typ) at fIN = 500kHz
range with high common mode rejection. The LTC2324- n Guaranteed Operation to 125°C 14 achieves ±1LSB INL typical, no missing codes at 14 n Single 3.3V or 5V Supply bits and 81dB SNR. n Low Drift (20ppm/°C Max) 2.048V or 4.096V The LTC2324-14 has an onboard low drift (20ppm/°C max) Internal Reference 2.048V or 4.096V temperature-compensated reference. n 1.8V to 2.5V I/O Voltages The LTC2324-14 also has a high speed SPI-compatible n CMOS or LVDS SPI-Compatible Serial I/O serial interface that supports CMOS or LVDS. The fast n Power Dissipation 40mW/Ch (Typ) 2Msps per channel throughput with no latency makes the n Small 52-Lead (7mm × 8mm) QFN Package LTC2324-14 ideally suited for a wide variety of high speed applications. The LTC2324-14 dissipates only 40mW per
applicaTions
channel and offers nap and sleep modes to reduce the n High Speed Data Acquisition Systems power consumption to 26μW for further power savings n Communications during inactive periods. n Optical Networking L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and ThinSOT is a trademark of Analog Devices, Inc. All other trademarks are the property of their n Multiphase Motor Control respective owners.
Typical applicaTion TRUE DIFFERENTIAL INPUTS
10µF 1µF
NO CONFIGURATION REQUIRED
3.3V OR 5V 1.8V TO 2.5V
32k Point FFT fSMPL = 2Msps, fIN = 500kHz IN+, IN–
VDD GND GND O 0 ARBITRARY DIFFERENTIAL VDD SNR = 82.3dB VDD VDD A + 14-BIT THD = –90.9dB IN1 CMOS/LVDS –20 A – S/H +SIGN SINAD = 81.6dB IN1 SDR/DDR SAR ADC REFBUFEN SFDR = 96.5dB –40 + 14-BIT SDO1 0V 0V AIN2 A – S/H +SIGN SDO2 IN2 SAR ADC SDO3 –60 LTC2324-14 SDO4 BIPOLAR UNIPOLAR + 14-BIT CLKOUT –80 V AIN3 DD VDD S/H +SIGN SCK A – IN3 SAR ADC AMPLITUDE (dBFS) –100 CNV SAMPLE 14-BIT A + IN4 CLOCK – S/H +SIGN –120 0V 0V AIN4 SAR ADC REF REFOUT1 REFOUT2 REFOUT3 REFOUT4 –140 0 0.2 0.4 0.6 0.8 1 FOUR SIMULTANEOUS 1µF 10µF 10µF 10µF 10µF FREQUENCY (MHz) SAMPLING CHANNELS 232414 TA01a 232414 TA01b 232414f For more information www.linear.com/LTC2324-14 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics ADC Timing Characteristics ADC Timing Characteristics Typical Performance Characteristics Pin Functions Pins that are the same for all digital I/O Modes CMOS data output option (CMOS/LVDS = low) LVDS data output option (CMOS/LVDS = high or FLOAT) Functional Block Diagram Timing Diagram Applications Information OVERVIEW CONVERTER OPERATION TRANSFER FUNCTION INPUT DRIVE CIRCUITS ADC REFERENCE DYNAMIC PERFORMANCE POWER CONSIDERATIONS TIMING AND CONTROL DIGITAL INTERFACE BOARD LAYOUT Package Description Typical Application Related Parts