Datasheet LTC2324-12 (Analog Devices)

LTC2324-12 Quad, 12-Bit + Sign, 2Msps/Ch Simultaneous Sampling ADC
FeaTures DescripTion
n
2Msps/Ch Throughput Rate
The LTC®2324-12 is a low noise, high speed quad 12-bit n
Four Simultaneously Sampling Channels
+ sign successive approximation register (SAR) ADC with n
Guaranteed 12-Bit, No Missing Codes
differential inputs and wide input common mode range. n
8VP-P Differential Inputs with Wide Input
Operating from a single 3.3V or 5V supply, the LTC2324-
Common Mode Range
12 has an 8VP-P differential input range, making it ideal n
78dB SNR (Typ) at fIN = 500kHz
for applications which require a wide dynamic range with n
–88dB THD (Typ) at fIN = 500kHz
high common mode rejection. The LTC2324-12 achieves n Guaranteed Operation to 125°C ±0.5LSB INL typical, no missing codes at 12 bits and n Single 3.3V or 5V Supply 78dB SNR. n Low Drift (20ppm/°C Max) 2.048V or 4.096V The LTC2324-12 has an onboard low drift (20ppm/°C max) Internal Reference 2.048V or 4.096V temperature-compensated reference. n 1.8V to 2.5V I/O Voltages The LTC2324-12 also has a high speed SPI-compatible n CMOS or LVDS SPI-Compatible Serial I/O serial interface that supports CMOS or LVDS. The fast n Power Dissipation 40mW/Ch (Typ) 2Msps per channel throughput with no latency makes the n Small 52-Lead (7mm × 8mm) QFN Package LTC2324-12 ideally suited for a wide variety of high speed applications. The LTC2324-12 dissipates only 40mW per
applicaTions
channel and offers nap and sleep modes to reduce the n High Speed Data Acquisition Systems power consumption to 26μW for further power savings n Communications during inactive periods. n Optical Networking L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and ThinSOT is a trademark of Analog Devices, Inc. All other trademarks are the property of their n Multiphase Motor Control respective owners.
Typical applicaTion 32k Point FFT f
10µF 1µF
SMPL = 2Msps, TRUE DIFFERENTIAL INPUTS f NO CONFIGURATION REQUIRED IN = 500kHz
3.3V OR 5V 1.8V TO 2.5V 0
IN+, IN–
SNR = 78.5dB VDD GND GND OV THD = –87.8dB ARBITRARY DIFFERENTIAL DD –20 SINAD = 78.2dB VDD VDD A + CMOS/LVDS SFDR = 95.9dB IN1 A – S/H 12-BIT + SIGN SDR/DDR IN1 SAR ADC –40 REFBUFEN A + IN2 12-BIT + SIGN SDO1 –60 0V 0V A – S/H IN2 SAR ADC SDO2 SDO3 –80 LTC2324-12 SDO4 BIPOLAR UNIPOLAR CLKOUT + AMPLITUDE (dBFS) V AIN3 SCK –100 DD VDD A – S/H 12-BIT + SIGN IN3 SAR ADC CNV SAMPLE –120 A + IN4 CLOCK A – S/H 12-BIT + SIGN SAR ADC 0V 0V IN4 –140 0 0.2 0.4 0.6 0.8 1 REF REFOUT1 REFOUT2 REFOUT3 REFOUT4 FREQUENCY (MHz) 232412 TA01b FOUR SIMULTANEOUS 1µF 10µF 10µF 10µF 10µF SAMPLING CHANNELS 232412 TA01a 232412fa For more information www.linear.com/LTC2324-12 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Related Parts