Datasheet LTC2320-16 (Analog Devices) - 10

LTC2320-16
PIN FUNCTIONS PINS THAT ARE THE SAME FOR ALL DIGITAL VDD (Pins 15, 21, 44, 52):
Power Supply. Bypass VDD to
I/O MODES
GND with a 10µF ceramic capacitor and a 0.1µF ceramic
A + –
capacitor close to the part. The VDD pins should be shorted
IN6 , AIN6 (Pins 2, 1):
Analog Differential Input Pins. Full-scale range (A + – together and driven from the same supply. IN6 – AIN6 ) is ±REFOUT3 voltage. These pins can be driven from V
+ –
DD to GND.
AIN2 , AIN2 (Pins 17, 16):
Analog Differential Input Pins. + –
GND (Pins 3, 7, 12, 18, 26, 32, 38, 46, 49):
Ground. Full-scale range (AIN2 – AIN2 ) is ±REFOUT1 voltage. These pins and exposed pad (Pin 53) must be tied directly These pins can be driven from VDD to GND. to a solid ground plane.
A + – IN1 , AIN1 (Pins 20, 19):
Analog Differential Input Pins. + –
A + –
Full-scale range (AIN1 – AIN1 ) is ±REFOUT1 voltage.
IN5 , AIN5 (Pins 5, 4):
Analog Differential Input Pins. Full-scale range (A + – These pins can be driven from VDD to GND. IN5 – AIN5 ) is ±REFOUT3 voltage. These pins can be driven from VDD to GND.
REFOUT1 (Pin 22):
Reference Buffer 1 Output. An onboard
REFOUT3 (Pin 6):
Reference Buffer 3 Output. An onboard buffer nominally outputs 4.096V to this pin. This pin is buffer nominally outputs 4.096V to this pin. This pin is referred to GND and should be decoupled closely to the referred to GND and should be decoupled closely to the pin with a 10µF (X5R, 0805 size) ceramic capacitor. The pin with a 10µF (X5R, 0805 size) ceramic capacitor. The internal buffer driving this pin may be disabled by ground- internal buffer driving this pin may be disabled by ground- ing the REFBUFEN pin. If the buffer is disabled, an external ing the REFBUFEN pin. If the buffer is disabled, an external reference may drive this pin in the range of 1.25V to 5V. reference may drive this pin in the range of 1.25V to 5V.
SDR
/
DDR (Pin 23):
Double Data Rate Input. Controls the
REF (Pin 8):
Common 4.096V reference output. Decouple frequency of SCK and CLKOUT. Tie to GND for the falling to GND with a 1μF low ESR ceramic capacitor. May be edge of SCK to shift each serial data output (Single Data overdriven with a single external reference to establish a Rate, SDR). Tie to OVDD to shift serial data output on each common reference for ADC cores 1 through 4. edge of SCK (Double Data Rate, DDR). CLKOUT will be a delayed version of SCK for both pin states.
REFOUT2 (Pin 9):
Reference Buffer 2 Output. An onboard buffer nominally outputs 4.096V to this pin. This pin is
CNV (Pin 24):
Convert Input. This pin, when high, defines referred to GND and should be decoupled closely to the the acquisition phase. When this pin is driven low, the pin with a 10µF (X5R, 0805 size) ceramic capacitor. The conversion phase is initiated and output data is clocked internal buffer driving this pin may be disabled by ground- out. This input must be driven at OVDD levels with a low ing the REFBUFEN pin. If the buffer is disabled, an external jitter pulse. This pin is unaffected by the CMOS/LVDS pin. reference may drive this pin in the range of 1.25V to 5V.
CMOS/LVDS (Pin 25):
I/O Mode Select. Ground this pin
A + –
to enable CMOS mode, tie to OVDD to enable LVDS mode.
IN4 , AIN4 (Pins 11, 10):
Analog Differential Input Pins. Full-scale range (A + – Float this pin to enable low power LVDS mode. IN4 – AIN4 ) is ±REFOUT2 voltage. These pins can be driven from VDD to GND.
OVDD (Pins 31, 37):
I/O Interface Digital Power. The range
A + –
of OVDD is 1.71V to 2.63V. This supply is nominally set
IN3 , AIN3 (Pins 14, 13):
Analog Differential Input Pins. Full-scale range (AIN3+ – A – to the same supply as the host interface (CMOS: 1.8V or IN3 ) is ±REFOUT2 voltage. These pins can be driven from V 2.5V, LVDS: 2.5V). Bypass OVDD to GND (Pins 32 and 38) DD to GND. with 0.1µF capacitors. 232016fb 10 For more information www.linear.com/LTC2320-16 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Related Parts .32673 Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics ADC Timing Characteristics ADC Timing Characteristics Typical Performance Characteristics Pin Functions CMOS data output option (CMOS/LVDS = low) LVDS data output option (CMOS/LVDS = high or FLOAT) Functional Block Diagram Timing Diagram Applications Information OVERVIEW CONVERTER OPERATION TRANSFER FUNCTION INPUT DRIVE CIRCUITS ADC REFERENCE DYNAMIC PERFORMANCE POWER CONSIDERATIONS TIMING AND CONTROL DIGITAL INTERFACE BOARD LAYOUT Package Description Typical Application Related Parts