Datasheet LTC2314-14 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | 14-Bit, 4.5Msps Serial Sampling ADC in TSOT |
| Páginas / Página | 22 / 8 — TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 5V, OVDD = 2.5V, … |
| Formato / tamaño de archivo | PDF / 679 Kb |
| Idioma del documento | Inglés |
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 5V, OVDD = 2.5V, fSMPL = 4.5Msps,. unless otherwise noted
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LTC2314-14
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 5V, OVDD = 2.5V, fSMPL = 4.5Msps, unless otherwise noted. Supply Current (IVDD) Output Supply Current (IOVDD) vs Supply Voltage (VDD) vs Output Supply Voltage (OVDD)
6.50 2.5 5Msps 6.25 2.0 6.00 5Msps f 5.75 SCK = 87.5MHz 1.5 5Msps fSCK = 87.5MHz 5.50 OPERATION NOT ALLOWED 1.0 5.25 3Msps SUPPLY CURRENT (mA) 3Msps 5.00 3Msps fSCK = 52.5MHz 0.5 OUTPUT SUPPLY CURRENT (mA) fSCK = 52.5MHz 4.75 4.50 0 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3 1.7 2.3 2.9 3.5 4.1 4.7 5.3 SUPPLY VOLTAGE (V) OUTPUT SUPPLY VOLTAGE (V) 231414 G17 231414 G18
PIN FUNCTIONS VDD (Pin 1):
Power Supply. The ranges of VDD are 2.7V
SDO (Pin 6):
Serial Data Output. The A/D conversion result to 3.6V and 4.75V to 5.25V. Bypass VDD to GND with a is shifted out on SDO as a serial data stream with the MSB 2.2µF ceramic chip capacitor. first through the LSB last. There is 1 cycle of conversion
REF (Pin 2):
Reference Input/Output. The REF pin volt- latency. Logic levels are determined by OVDD. age defines the input span of the ADC, 0V to VREF. By
SCK (Pin 7):
Serial Data Clock Input. The SCK serial clock default, REF is an output pin and produces a reference falling edge advances the conversion process and outputs voltage VREF of either 2.048V or 4.096V depending on a bit of the serialized conversion result, MSB first to LSB VDD (see Table 2). Bypass to GND with a 2.2µF, low ESR, last. SDO data transitions on the falling edge of SCK. A high quality ceramic chip capacitor. The REF pin may be continuous or burst clock may be used. Logic levels are overdriven with a voltage at least 50mV higher than the determined by OVDD. internal reference voltage output.
CS (Pin 8):
Chip Select Input. This active low signal starts
GND (Pin 3):
Ground. The GND pin must be tied directly a conversion on the falling edge and frames the serial data to a solid ground plane. transfer. Bringing CS high places the sample-and-hold
A
into sample mode and also forces the SDO pin into high
IN (Pin 4):
Analog Input. AIN is a single-ended input with respect to GND with a range from 0V to V impedance. Logic levels are determined by OVDD. REF.
OVDD (Pin 5):
I/O Interface Digital Power. The OVDD range is 1.71V to 5.25V. This supply is nominally set to the same supply as the host interface (1.8V, 2.5V, 3.3V or 5V). Bypass to GND with a 2.2µF ceramic chip capacitor. 231414fa 8 For more information www.linear.com/LTC2314-14
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 5V, OVDD = 2.5V, fSMPL = 4.5Msps, unless otherwise noted. Supply Current (IVDD) Output Supply Current (IOVDD) vs Supply Voltage (VDD) vs Output Supply Voltage (OVDD)
6.50 2.5 5Msps 6.25 2.0 6.00 5Msps f 5.75 SCK = 87.5MHz 1.5 5Msps fSCK = 87.5MHz 5.50 OPERATION NOT ALLOWED 1.0 5.25 3Msps SUPPLY CURRENT (mA) 3Msps 5.00 3Msps fSCK = 52.5MHz 0.5 OUTPUT SUPPLY CURRENT (mA) fSCK = 52.5MHz 4.75 4.50 0 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3 1.7 2.3 2.9 3.5 4.1 4.7 5.3 SUPPLY VOLTAGE (V) OUTPUT SUPPLY VOLTAGE (V) 231414 G17 231414 G18
PIN FUNCTIONS VDD (Pin 1):
Power Supply. The ranges of VDD are 2.7V
SDO (Pin 6):
Serial Data Output. The A/D conversion result to 3.6V and 4.75V to 5.25V. Bypass VDD to GND with a is shifted out on SDO as a serial data stream with the MSB 2.2µF ceramic chip capacitor. first through the LSB last. There is 1 cycle of conversion
REF (Pin 2):
Reference Input/Output. The REF pin volt- latency. Logic levels are determined by OVDD. age defines the input span of the ADC, 0V to VREF. By
SCK (Pin 7):
Serial Data Clock Input. The SCK serial clock default, REF is an output pin and produces a reference falling edge advances the conversion process and outputs voltage VREF of either 2.048V or 4.096V depending on a bit of the serialized conversion result, MSB first to LSB VDD (see Table 2). Bypass to GND with a 2.2µF, low ESR, last. SDO data transitions on the falling edge of SCK. A high quality ceramic chip capacitor. The REF pin may be continuous or burst clock may be used. Logic levels are overdriven with a voltage at least 50mV higher than the determined by OVDD. internal reference voltage output.
CS (Pin 8):
Chip Select Input. This active low signal starts
GND (Pin 3):
Ground. The GND pin must be tied directly a conversion on the falling edge and frames the serial data to a solid ground plane. transfer. Bringing CS high places the sample-and-hold
A
into sample mode and also forces the SDO pin into high
IN (Pin 4):
Analog Input. AIN is a single-ended input with respect to GND with a range from 0V to V impedance. Logic levels are determined by OVDD. REF.
OVDD (Pin 5):
I/O Interface Digital Power. The OVDD range is 1.71V to 5.25V. This supply is nominally set to the same supply as the host interface (1.8V, 2.5V, 3.3V or 5V). Bypass to GND with a 2.2µF ceramic chip capacitor. 231414fa 8 For more information www.linear.com/LTC2314-14