Datasheet LTC2312-14 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | 14-Bit, 500ksps Serial Sampling ADC in TSOT |
| Páginas / Página | 22 / 9 — BLOCK DIAGRAM. TIMING DIAGRAMS. Figure 1. SDO Enabled After CONV. Figure … |
| Formato / tamaño de archivo | PDF / 635 Kb |
| Idioma del documento | Inglés |
BLOCK DIAGRAM. TIMING DIAGRAMS. Figure 1. SDO Enabled After CONV. Figure 2. SDO Into Hi-Z After CONV
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- LTC2312CTS8-14#PBF LTC2312CTS8-14#TRMPBF LTC2312CTS8-14#TRMPBF LTC2312CTS8-14#TRPBF LTC2312CTS8-14#TRPBF LTC2312HTS8-14#PBF LTC2312HTS8-14#TRMPBF LTC2312HTS8-14#TRMPBF LTC2312HTS8-14#TRPBF LTC2312HTS8-14#TRPBF LTC2312ITS8-14#PBF LTC2312ITS8-14#TRMPBF LTC2312ITS8-14#TRMPBF LTC2312ITS8-14#TRPBF LTC2312ITS8-14#TRPBF
Versión de texto del documento
LTC2312-14
BLOCK DIAGRAM
2.2µF 2.2µF ANALOG SUPPLY I/O INTERFACE SUPPLY 3V OR 5V RANGE 1.8V TO 5V 1 5 VDD OVDD 2.5V LDO A ANALOG IN INPUT RANGE 4 + THREE-STATE SDO 0V TO VREF SERIAL S/H 14-BIT SAR ADC 6 OUTPUT – PORT REF SCK 2 7 TIMING 2.2µF GND 1.024V CONV 2×/4× LOGIC 3 BANDGAP 8 TS8 PACKAGE 231214 BD ALL CAPACITORS UNLESS NOTED ARE HIGH QUALITY, CERAMIC CHIP TYPE
TIMING DIAGRAMS
t3 t8 CONV OVDD/2 CONV OVDD/2 Hi-Z VOH Hi-Z SDO MSB SDO VOL
Figure 1. SDO Enabled After CONV
↓
Figure 2. SDO Into Hi-Z After CONV
↑ 231214 TD01 231214 TD02 t7 t4 SCK SCK OVDD/2 OVDD/2 V V OH OH SDO V SDO OL VOL
Figure 3. SDO Data Valid Hold After SCK
↓
Figure 4. SDO Data Valid Access After SCK
↓ 231214 TD03 231214 TD04 231214fa For more information www.linear.com/LTC2312-14 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Reference Input/Output Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagrams Applications Information Package Description Related Parts
BLOCK DIAGRAM
2.2µF 2.2µF ANALOG SUPPLY I/O INTERFACE SUPPLY 3V OR 5V RANGE 1.8V TO 5V 1 5 VDD OVDD 2.5V LDO A ANALOG IN INPUT RANGE 4 + THREE-STATE SDO 0V TO VREF SERIAL S/H 14-BIT SAR ADC 6 OUTPUT – PORT REF SCK 2 7 TIMING 2.2µF GND 1.024V CONV 2×/4× LOGIC 3 BANDGAP 8 TS8 PACKAGE 231214 BD ALL CAPACITORS UNLESS NOTED ARE HIGH QUALITY, CERAMIC CHIP TYPE
TIMING DIAGRAMS
t3 t8 CONV OVDD/2 CONV OVDD/2 Hi-Z VOH Hi-Z SDO MSB SDO VOL
Figure 1. SDO Enabled After CONV
↓
Figure 2. SDO Into Hi-Z After CONV
↑ 231214 TD01 231214 TD02 t7 t4 SCK SCK OVDD/2 OVDD/2 V V OH OH SDO V SDO OL VOL
Figure 3. SDO Data Valid Hold After SCK
↓
Figure 4. SDO Data Valid Access After SCK
↓ 231214 TD03 231214 TD04 231214fa For more information www.linear.com/LTC2312-14 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Reference Input/Output Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagrams Applications Information Package Description Related Parts