Datasheet LTC2311-12 (Analog Devices) - 9

LTC2311-12
pin FuncTions GND (Pins 1, 5, 8, 11):
Ground. These pins and the exposed
OVDD (Pin 12):
I/O Interface Digital Power. The range of pad (Pin 17) must be tied directly to a solid ground plane. OVDD is 1.71V to 2.5V. This supply is nominally set to the
REFIN (Pin 2):
Reference Buffer 1.25V Input/Output. An same supply as the host interface (CMOS: 1.8V or 2.5V, onboard buffer nominally outputs 1.25V to this pin. This LVDS: 2.5V). Bypass OVDD to GND with a 1μF ceramic pin should be decoupled closely to the pin (no vias) with capacitor close to the OVDD pin. a 10μF (X5R, 0805 size) ceramic capacitor. The internal
Exposed Pad (Pin 17):
Ground. Solder this pad to ground. buffer driving this pin may be overdriven with an external reference. The REFIN pin, when pulled to GND disables
CMOS I/O Mode
the REFOUT pin buffer allowing an external reference to
SDO+ (Pin 14):
Serial Data Output. The conversion result drive REFOUT directly. is shifted MSB first on each falling edge of SCK. The result
REFOUT (Pin 3):
Reference Buffer Output. An onboard is output on SDO+. The logic level is determined by OVDD. buffer nominally outputs 4.096V to this pin. This pin should Do not connect SDO–. (Pin 13) be decoupled closely to the pin (no vias) with a 10μF (X5R,
SCK+ (Pin 16):
Serial Data Clock Input. The falling edge 0805 size) ceramic capacitor. The internal buffer driving of this clock shifts the conversion result MSB first onto this pin may be disabled by grounding the REFIN pin. If the SDO pins. Drive SCK+ with a single-ended clock. The the buffer is disabled, an external reference may drive this logic level is determined by OV pin in the range of 1.25V to V DD. Do not connect SCK–. DD. (Pin 15)
VDD (Pin 4):
Power Supply. Bypass VDD to GND with a 1µF ceramic capacitor close to the V
LVDS I/O Mode
DD pin.
A SDO+, SDO– (Pins 14, 13):
Serial Data Output. The con-
IN+, AIN– (Pins 6, 7):
Analog Differential Input Pins. Full- scale range (A version result is shifted MSB first on each falling edge of IN+ to AIN–) is ±REFOUT voltage. These pins can be driven from V SCK. The result is output differentially on SDO+ and SDO–. DD to GND. These pins must be differentially terminated by an external
CNV (Pin 9):
Convert Input. This pin, when high, defines 100Ω resistor at the receiver (FPGA). the sampling phase. When this pin is driven low, the con- version phase is initiated and output data is clocked out.
SCK+, SCK– (Pins 16, 15):
Serial Data Clock Input. The This input pin is a TTL style input typically driven at OV falling edge of this clock shifts the conversion result MSB DD levels with a low jitter pulse, but it is bound to V first onto the SDO pins. Drive SCK+ and SCK– with a dif- DD levels. This pin is unaffected by the CMOS/LVDS pin. ferential clock. These pins must be differentially terminated by an external 100Ω resistor at the receiver (ADC).
CMOS/LVDS (Pin 10):
I/O mode select. Ground this pin to enable CMOS mode, tie to OVDD to enable LVDS mode. Float this pin to enable low power LVDS mode. 231112f For more information www.linear.com/LTC2311-12 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Functional Block Diagram Timing Diagram Applications Information Package Description Typical Application Related Parts