Datasheet LTC2301, LTC2305 (Analog Devices) - 10
| Fabricante | Analog Devices |
| Descripción | 2-Channel, 12-Bit ADCs with I2C Compatible Interface |
| Páginas / Página | 26 / 10 — PIN FUNCTIONS (LTC2305) GND (Pins 1, 4, 9):. REFCOMP (Pin 8):. SDA (Pin … |
| Formato / tamaño de archivo | PDF / 907 Kb |
| Idioma del documento | Inglés |
PIN FUNCTIONS (LTC2305) GND (Pins 1, 4, 9):. REFCOMP (Pin 8):. SDA (Pin 2):. VDD (Pin 10):. SCL (Pin 3):. AD1 (Pin 11):
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Versión de texto del documento
LTC2301/LTC2305
PIN FUNCTIONS (LTC2305) GND (Pins 1, 4, 9):
Ground. All GND pins must be con-
REFCOMP (Pin 8):
Reference Buffer Output. Bypass to nected to a solid ground plane. GND with 10μF and 0.1μF ceramic capacitors in parallel. Nominal output voltage is 4.096V. The internal reference
SDA (Pin 2):
Bidirectional Serial Data Line of the I2C In- buffer driving this pin is disabled by grounding V terface. In transmitter mode (read), the conversion result REF, al- lowing REFCOMP to be overdriven by an external source is output at the SDA pin, while in receiver mode (write), (see Figure 5c). the DIN word is input at the SDA pin to confi gure the ADC. The pin is high impedance during the data input mode and
VDD (Pin 10):
5V Analog Supply. The range of VDD is 4.75V is an open drain output (requires an appropriate pull-up to 5.25V. Bypass VDD to GND with 10μF and 0.1μF ceramic device to VDD) during the data output mode. capacitors in parallel.
SCL (Pin 3):
Serial Clock Pin of the I2C Interface. The
AD1 (Pin 11):
Chip Address Control Pin. This pin is con- LTC2305 can only act as a slave and the SCL pin only ac- fi gured as a three-state (LOW, HIGH, fl oating) address cepts an external serial clock. Data is shifted into the SDA control bit for the device I2C address. See Table 2 for pin on the rising edges of the SCL clock and output through address selection. the SDA pin on the falling edges of the SCL clock.
AD0 (Pin 12):
Chip Address Control Pin. This pin is con-
CH0-CH1 (Pins 5, 6):
Channel 0 and Channel 1 Analog fi gured as a three-state (LOW, HIGH, fl oating) address Inputs. CH0 and CH1 can be confi gured as single-ended control bit for the device I2C address. See Table 2 for or differential input channels. See the Analog Input Multi- address selection. plexer section.
GND (Pin 13 – DFN Package Only):
Exposed Pad Ground.
VREF (Pin 7):
2.5V Reference Output. Bypass to GND with Must be soldered directly to ground plane. a minimum 2.2μF ceramic capacitor. The internal refer- ence may be overdriven by an external 2.5V reference at this pin. 23015fb 10
PIN FUNCTIONS (LTC2305) GND (Pins 1, 4, 9):
Ground. All GND pins must be con-
REFCOMP (Pin 8):
Reference Buffer Output. Bypass to nected to a solid ground plane. GND with 10μF and 0.1μF ceramic capacitors in parallel. Nominal output voltage is 4.096V. The internal reference
SDA (Pin 2):
Bidirectional Serial Data Line of the I2C In- buffer driving this pin is disabled by grounding V terface. In transmitter mode (read), the conversion result REF, al- lowing REFCOMP to be overdriven by an external source is output at the SDA pin, while in receiver mode (write), (see Figure 5c). the DIN word is input at the SDA pin to confi gure the ADC. The pin is high impedance during the data input mode and
VDD (Pin 10):
5V Analog Supply. The range of VDD is 4.75V is an open drain output (requires an appropriate pull-up to 5.25V. Bypass VDD to GND with 10μF and 0.1μF ceramic device to VDD) during the data output mode. capacitors in parallel.
SCL (Pin 3):
Serial Clock Pin of the I2C Interface. The
AD1 (Pin 11):
Chip Address Control Pin. This pin is con- LTC2305 can only act as a slave and the SCL pin only ac- fi gured as a three-state (LOW, HIGH, fl oating) address cepts an external serial clock. Data is shifted into the SDA control bit for the device I2C address. See Table 2 for pin on the rising edges of the SCL clock and output through address selection. the SDA pin on the falling edges of the SCL clock.
AD0 (Pin 12):
Chip Address Control Pin. This pin is con-
CH0-CH1 (Pins 5, 6):
Channel 0 and Channel 1 Analog fi gured as a three-state (LOW, HIGH, fl oating) address Inputs. CH0 and CH1 can be confi gured as single-ended control bit for the device I2C address. See Table 2 for or differential input channels. See the Analog Input Multi- address selection. plexer section.
GND (Pin 13 – DFN Package Only):
Exposed Pad Ground.
VREF (Pin 7):
2.5V Reference Output. Bypass to GND with Must be soldered directly to ground plane. a minimum 2.2μF ceramic capacitor. The internal refer- ence may be overdriven by an external 2.5V reference at this pin. 23015fb 10