Datasheet LTC2289 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | Dual 10-Bit, 80Msps Low Noise 3V ADC |
| Páginas / Página | 24 / 9 — PI FU CTIO S. SHDNA (Pin 59):. CMA (Pin 61):. SENSEA (Pin 62):. MODE (Pin … |
| Formato / tamaño de archivo | PDF / 677 Kb |
| Idioma del documento | Inglés |
PI FU CTIO S. SHDNA (Pin 59):. CMA (Pin 61):. SENSEA (Pin 62):. MODE (Pin 60):. GND (Exposed Pad) (Pin 65):
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LTC2289
U U U PI FU CTIO S SHDNA (Pin 59):
Channel A Shutdown Mode Selection lizer on. VDD selects 2’s complement output format and Pin. Connecting SHDNA to GND and OEA to GND results turns the clock duty cycle stabilizer off. in normal operation with the outputs enabled. Connecting
V
SHDNA to GND and OEA to V
CMA (Pin 61):
Channel A 1.5V Output and Input Common DD results in normal opera- Mode Bias. Bypass to ground with 2.2µF ceramic chip tion with the outputs at high impedance. Connecting capacitor. Do not connect to V SHDNA to V CMB. DD and OEA to GND results in nap mode with the outputs at high impedance. Connecting SHDNA to V
SENSEA (Pin 62):
Channel A Reference Programming Pin. DD and OEA to V Connecting SENSEA to V DD results in sleep mode with the outputs at CMA selects the internal reference high impedance. and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than
MODE (Pin 60):
Output Format and Clock Duty Cycle 0.5V and less than 1V applied to SENSEA selects an input Stabilizer Selection Pin. Note that MODE controls both range of ±V channels. Connecting MODE to GND selects offset binary SENSEA. ±1V is the largest valid input range. output format and turns the clock duty cycle stabilizer off.
GND (Exposed Pad) (Pin 65):
ADC Power Ground. The 1/3 V Exposed Pad on the bottom of the package needs to be DD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 V soldered to ground. DD selects 2’s comple- ment output format and turns the clock duty cycle stabi-
U U W FUNCTIONAL BLOCK DIAGRA
A + IN INPUT FIRST PIPELINED SECOND PIPELINED THIRD PIPELINED FOURTH PIPELINED FIFTH PIPELINED SIXTH PIPELINED – S/H ADC STAGE ADC STAGE ADC STAGE ADC STAGE ADC STAGE ADC STAGE AIN VCM 1.5V REFERENCE SHIFT REGISTER 2.2µF AND CORRECTION RANGE SELECT REFH REFL INTERNAL CLOCK SIGNALS OVDD REF SENSE BUF OF D9 DIFF CLOCK/DUTY CONTROL OUTPUT REF CYCLE LOGIC • DRIVERS AMP CONTROL • • D0 REFH 0.1µF REFL 2289 F01 OGND CLK MODE SHDN OE 2.2µF 1µF 1µF
Figure 1. Functional Block Diagram (Only One Channel is Shown)
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U U U PI FU CTIO S SHDNA (Pin 59):
Channel A Shutdown Mode Selection lizer on. VDD selects 2’s complement output format and Pin. Connecting SHDNA to GND and OEA to GND results turns the clock duty cycle stabilizer off. in normal operation with the outputs enabled. Connecting
V
SHDNA to GND and OEA to V
CMA (Pin 61):
Channel A 1.5V Output and Input Common DD results in normal opera- Mode Bias. Bypass to ground with 2.2µF ceramic chip tion with the outputs at high impedance. Connecting capacitor. Do not connect to V SHDNA to V CMB. DD and OEA to GND results in nap mode with the outputs at high impedance. Connecting SHDNA to V
SENSEA (Pin 62):
Channel A Reference Programming Pin. DD and OEA to V Connecting SENSEA to V DD results in sleep mode with the outputs at CMA selects the internal reference high impedance. and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than
MODE (Pin 60):
Output Format and Clock Duty Cycle 0.5V and less than 1V applied to SENSEA selects an input Stabilizer Selection Pin. Note that MODE controls both range of ±V channels. Connecting MODE to GND selects offset binary SENSEA. ±1V is the largest valid input range. output format and turns the clock duty cycle stabilizer off.
GND (Exposed Pad) (Pin 65):
ADC Power Ground. The 1/3 V Exposed Pad on the bottom of the package needs to be DD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 V soldered to ground. DD selects 2’s comple- ment output format and turns the clock duty cycle stabi-
U U W FUNCTIONAL BLOCK DIAGRA
A + IN INPUT FIRST PIPELINED SECOND PIPELINED THIRD PIPELINED FOURTH PIPELINED FIFTH PIPELINED SIXTH PIPELINED – S/H ADC STAGE ADC STAGE ADC STAGE ADC STAGE ADC STAGE ADC STAGE AIN VCM 1.5V REFERENCE SHIFT REGISTER 2.2µF AND CORRECTION RANGE SELECT REFH REFL INTERNAL CLOCK SIGNALS OVDD REF SENSE BUF OF D9 DIFF CLOCK/DUTY CONTROL OUTPUT REF CYCLE LOGIC • DRIVERS AMP CONTROL • • D0 REFH 0.1µF REFL 2289 F01 OGND CLK MODE SHDN OE 2.2µF 1µF 1µF
Figure 1. Functional Block Diagram (Only One Channel is Shown)
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