Datasheet LTC2283 (Analog Devices) - 8

LTC2283
PIN FUNCTIONS A + INA (Pin 1):
Channel A Positive Differential Analog and a ±0.5V input range. VDD selects the internal reference Input. and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSEB selects an input
A – INA (Pin 2):
Channel A Negative Differential Analog range of ±V Input. SENSEB. ±1V is the largest valid input range.
V REFHA (Pins 3, 4):
Channel A High Reference. Short to-
CMB (Pin 20):
Channel B 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2μF ceramic chip gether and bypass to Pins 5, 6 with a 0.1μF ceramic chip capacitor. Do not connect to V capacitor as close to the pin as possible. Also bypass to CMA. Pins 5, 6 with an additional 2.2μF ceramic chip capacitor
MUX (Pin 21):
Digital Output Multiplexer Control. If MUX and to ground with a 1μF ceramic chip capacitor. is High, Channel A comes out on DA0-DA11; Channel B comes out on DB0-DB11. If MUX is Low, the output bus-
REFLA (Pins 5, 6):
Channel A Low Reference. Short to- ses are swapped and Channel A comes out on DB0-DB11; gether and bypass to Pins 3, 4 with a 0.1μF ceramic chip Channel B comes out on DA0-DA11. To multiplex both capacitor as close to the pin as possible. Also bypass to channels onto a single output bus, connect MUX, CLKA Pins 3, 4 with an additional 2.2μF ceramic chip capacitor and CLKB together. (This is not recommended at clock and to ground with a 1μF ceramic chip capacitor. frequencies above 80Msps.)
VDD (Pins 7, 10, 18, 63):
Analog 3V Supply. Bypass to
SHDNB (Pin 22):
Channel B Shutdown Mode Selection GND with 0.1μF ceramic chip capacitors. Pin. Connecting SHDNB to GND and OEB to GND results
CLKA (Pin 8):
Channel A Clock Input. The input sample in normal operation with the outputs enabled. Connecting starts on the positive edge. SHDNB to GND and OEB to VDD results in normal operation
CLKB (Pin 9):
Channel B Clock Input. The input sample with the outputs at high impedance. Connecting SHDNB starts on the positive edge. to VDD and OEB to GND results in nap mode with the outputs at high impedance. Connecting SHDNB to VDD
REFLB (Pins 11, 12):
Channel B Low Reference. Short and OEB to VDD results in sleep mode with the outputs together and bypass to Pins 13, 14 with a 0.1μF ceramic at high impedance. chip capacitor as close to the pin as possible. Also by- pass to Pins 13, 14 with an additional 2.2μF ceramic
OEB (Pin 23):
Channel B Output Enable Pin. Refer to chip capacitor and to ground with a 1μF ceramic chip SHDNB pin function. capacitor.
NC (Pins 24, 25, 41, 42):
Do not connect these pins.
REFHB (Pins 13, 14):
Channel B High Reference. Short
DB0 – DB11 (Pins 26 to 30, 33 to 39):
Channel B Digital together and bypass to Pins 11, 12 with a 0.1μF ceramic Outputs. DB11 is the MSB. chip capacitor as close to the pin as possible. Also by-
OGND (Pins 31, 50):
Output Driver Ground. pass to Pins 11, 12 with an additional 2.2μF ceramic chip capacitor and to ground with a 1μF ceramic chip
OVDD (Pins 32, 49):
Positive Supply for the Output Drivers. capacitor. Bypass to ground with 0.1μF ceramic chip capacitor.
A – INB (Pin 15):
Channel B Negative Differential Analog
CLKOUT (Pin 40):
Data Ready Clock Output. Latch data Input. on the falling edge of CLKOUT. CLKOUT is derived from CLKB. Tie CLKA to CLKB for simultaneous operation.
A + INB (Pin 16):
Channel B Positive Differential Analog Input.
DA0 – DA11 (Pins 43 to 48, 51 to 56):
Channel A Digital Outputs. DA11 is the MSB.
GND (Pins 17, 64):
ADC Power Ground.
OF (Pin 57):
Overfl ow/Underfl ow Output. High when an
SENSEB (Pin 19):
Channel B Reference Programming Pin. overfl ow or underfl ow has occurred on either Channel A Connecting SENSEB to VCMB selects the internal reference or Channel B. 2283fb 8