Datasheet LTC2282 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | Dual 12-Bit, 105Msps Low Power 3V ADC |
| Páginas / Página | 24 / 9 — PIN FUNCTIONS. SHDNA (Pin 59):. CMA (Pin 61):. SENSEA (Pin 62):. MODE … |
| Formato / tamaño de archivo | PDF / 475 Kb |
| Idioma del documento | Inglés |
PIN FUNCTIONS. SHDNA (Pin 59):. CMA (Pin 61):. SENSEA (Pin 62):. MODE (Pin 60):. Exposed Pad (Pin 65):. FUNCTIONAL BLOCK DIAGRAM
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LTC2282
PIN FUNCTIONS SHDNA (Pin 59):
Channel A Shutdown Mode Selection stabilizer on. VDD selects 2’s complement output format Pin. Connecting SHDNA to GND and OEA to GND results and turns the clock duty cycle stabilizer off. in normal operation with the outputs enabled. Connecting
V
SHDNA to GND and OEA to V
CMA (Pin 61):
Channel A 1.5V Output and Input Common DD results in normal operation Mode Bias. Bypass to ground with a 2.2μF ceramic chip with the outputs at high impedance. Connecting SHDNA capacitor. Do not connect to V to V CMB. DD and OEA to GND results in nap mode with the outputs at high impedance. Connecting SHDNA to V
SENSEA (Pin 62):
Channel A Reference Programming Pin. DD and OEA to V Connecting SENSEA to V DD results in sleep mode with the outputs CMA selects the internal reference at high impedance. and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than
MODE (Pin 60):
Output Format and Clock Duty Cycle 0.5V and less than 1V applied to SENSEA selects an input Stabilizer Selection Pin. Note that MODE controls both range of ±V channels. Connecting MODE to GND selects offset binary SENSEA. ±1V is the largest valid input range. output format and turns the clock duty cycle stabilizer
Exposed Pad (Pin 65):
ADC Power Ground. The Exposed off. 1/3 V Pad on the bottom of the package needs to be soldered DD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 V to ground. DD selects 2’s complement output format and turns the clock duty cycle
FUNCTIONAL BLOCK DIAGRAM
A + IN INPUT FIRST PIPELINED SECOND PIPELINED THIRD PIPELINED FOURTH PIPELINED FIFTH PIPELINED SIXTH PIPELINED – S/H ADC STAGE ADC STAGE ADC STAGE ADC STAGE ADC STAGE ADC STAGE AIN VCM 1.5V REFERENCE SHIFT REGISTER 2.2μF AND CORRECTION RANGE SELECT REFH REFL INTERNAL CLOCK SIGNALS OVDD REF SENSE BUF OF D11 DIFF CLOCK/DUTY CONTROL OUTPUT REF CYCLE LOGIC • DRIVERS AMP CONTROL • • D0 REFH 0.1μF REFL 2282 F01 OGND CLK MODE SHDN OE 2.2μF 1μF 1μF
Figure 1. Functional Block Diagram (Only One Channel is Shown)
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PIN FUNCTIONS SHDNA (Pin 59):
Channel A Shutdown Mode Selection stabilizer on. VDD selects 2’s complement output format Pin. Connecting SHDNA to GND and OEA to GND results and turns the clock duty cycle stabilizer off. in normal operation with the outputs enabled. Connecting
V
SHDNA to GND and OEA to V
CMA (Pin 61):
Channel A 1.5V Output and Input Common DD results in normal operation Mode Bias. Bypass to ground with a 2.2μF ceramic chip with the outputs at high impedance. Connecting SHDNA capacitor. Do not connect to V to V CMB. DD and OEA to GND results in nap mode with the outputs at high impedance. Connecting SHDNA to V
SENSEA (Pin 62):
Channel A Reference Programming Pin. DD and OEA to V Connecting SENSEA to V DD results in sleep mode with the outputs CMA selects the internal reference at high impedance. and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than
MODE (Pin 60):
Output Format and Clock Duty Cycle 0.5V and less than 1V applied to SENSEA selects an input Stabilizer Selection Pin. Note that MODE controls both range of ±V channels. Connecting MODE to GND selects offset binary SENSEA. ±1V is the largest valid input range. output format and turns the clock duty cycle stabilizer
Exposed Pad (Pin 65):
ADC Power Ground. The Exposed off. 1/3 V Pad on the bottom of the package needs to be soldered DD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 V to ground. DD selects 2’s complement output format and turns the clock duty cycle
FUNCTIONAL BLOCK DIAGRAM
A + IN INPUT FIRST PIPELINED SECOND PIPELINED THIRD PIPELINED FOURTH PIPELINED FIFTH PIPELINED SIXTH PIPELINED – S/H ADC STAGE ADC STAGE ADC STAGE ADC STAGE ADC STAGE ADC STAGE AIN VCM 1.5V REFERENCE SHIFT REGISTER 2.2μF AND CORRECTION RANGE SELECT REFH REFL INTERNAL CLOCK SIGNALS OVDD REF SENSE BUF OF D11 DIFF CLOCK/DUTY CONTROL OUTPUT REF CYCLE LOGIC • DRIVERS AMP CONTROL • • D0 REFH 0.1μF REFL 2282 F01 OGND CLK MODE SHDN OE 2.2μF 1μF 1μF
Figure 1. Functional Block Diagram (Only One Channel is Shown)
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