Datasheet LTC2274 (Analog Devices) - 6

LTC2274
The POWER REQUIREMENTS
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. AIN = –1dBFS. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Analog Supply Voltage l 3.135 3.3 3.465 V PSHDN Shutdown Power SHDN Pins = VDD 5 mW OVDD Output Supply Range CMLOUT Directly-Coupled 50Ω to OVDD (Note 7) l 1.2 VDD V CMLOUT Directly-Coupled 100Ω Differential (Note 7) l 1.4 VDD V CMLOUT AC-Coupled (Note 7) l 1.4 VDD V IVDD Analog Supply Current DC Input l 394 450 mA IOVDD Output Supply Current CMLOUT Directly-Coupled, 50Ω to 0VDD 8 mA CMLOUT Directly-Coupled 100Ω Differential 16 mA CMLOUT AC-Coupled 16 mA PDIS Power Dissipation DC Input l 1300 1485 mW
TIMING CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 9) l 20 105 MHz tCONV Conversion Period 1/fS s tL ENC Clock Low Time (Note 7) l 3.1 4.762 25 ns tH ENC Clock High Time (Note 7) l 3.1 4.762 25 ns tAP Sample-and-Hold Aperture Delay 0.7 ns tBIT, UI Period of a Serial Bit tCONV/20 s tJIT Total Jitter of CMLOUT± (P-P) BER = 1E–12 (Note 7) l 0.35 UI tR, tF Differential Rise and Fall Time of CMLOUT± (20% to 80%) RTERM = 50Ω, CL = 2pF l 50 110 ps (Note 7) tSU SYNC to ENC Clock Setup Time (Note 7) l 2 ns tHD ENC Clock to SYNC Hold Time (Note 7) l 2.5 ns tCS ENC Clock to SYNC Delay (Note 7) l tHD tCONV – tSU ns LATP Pipeline Latency 9 Cycles LATSC Latency from SYNC Active to COMMA Out 3 Cycles LATSD Latency from SYNC Release to DATA Out 2 Cycles
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 6:
Offset error is the offset voltage measured from –1/2LSB when the may cause permanent damage to the device. Exposure to any Absolute output code fl ickers between 0000 0000 0000 0000 and 1111 1111 1111 Maximum Rating condition for extended periods may affect device 1111 in 2’s complement output mode. reliability and lifetime.
Note 7:
Guaranteed by design, not subject to test.
Note 2:
All voltage values are with respect to GND (unless otherwise
Note 8:
VDD = 3.3V, fSAMPLE = 105MHz input range = 2.25VP-P with noted). differential drive.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 9:
Recommended operating conditions. will be clamped by internal diodes. This product can handle input currents
Note 10:
The dynamic current of the switched capacitors analog inputs of greater than 100mA below GND or above VDD without latchup. can be large compared to the leakage current and will vary with the sample
Note 4:
VDD = 3.3V, fSAMPLE = 105MHz differential ENC+/ENC– = 2VP-P sine rate. wave with 1.6V common mode, input range = 2.25VP-P with differential
Note 11:
Leakage current will have higher transient current at power up. drive (PGA = 0), unless otherwise specifi ed. Keep drive resistance at or below 1k.
Note 5:
Integral nonlinearity is defi ned as the deviation of a code from a “best fi t straight line” to the transfer curve. The deviation is measured from the center of the quantization band. 2274fb 6