Datasheet LTC2268-14, LTC2267-14, LTC2266-14 (Analog Devices)

LTC2268-14/ LTC2267-14/LTC2266-14 14-Bit, 125Msps/105Msps/ 80Msps Low Power Dual ADCs
FeaTures DescripTion
n
2-Channel Simultaneous Sampling ADC
The LTC®2268-14/LTC2267-14/LTC2266-14 are 2-channel, n
73.1dB SNR
simultaneous sampling 14-bit A/D converters designed n
88dB SFDR
for digitizing high frequency, wide dynamic range signals. n Low Power: 299mW/243mW/203mW Total They are perfect for demanding communications applica- n 150mW/121mW/101mW Per Channel tions with AC performance that includes 73.1dB SNR and n Single 1.8V Supply 88dB spurious free dynamic range (SFDR). Ultralow jitter n Serial LVDS Outputs: 1 or 2 Bits Per Channel of 0.15psRMS allows undersampling of IF frequencies with n Selectable Input Ranges: 1VP-P to 2VP-P excellent noise performance. n 800MHz Full Power Bandwidth S/H DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) n Shutdown and Nap Modes and no missing codes over temperature. The transition n Serial SPI Port for Configuration noise is a low 1.2LSB n RMS. Pin Compatible 14-Bit and 12-Bit Versions n 40-Pin (6mm × 6mm) QFN Package The digital outputs are serial LVDS to minimize the num- ber of data lines. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit
applicaTions
per channel option (1-lane mode). The LVDS drivers have n Communications optional internal termination and adjustable output levels n Cellular Base Stations to ensure clean signal integrity. n Software Defined Radios The ENC+ and ENC– inputs may be driven differentially n Portable Medical Imaging or single-ended with a sine wave, PECL, LVDS, TTL, or n Multichannel Data Acquisition CMOS inputs. An internal clock duty cycle stabilizer al- n Nondestructive Testing lows high performance at full speed for a wide range of L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear clock duty cycles. Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion LTC2268-14, 125Msps,
1.8V 1.8V
2-Tone FFT, fIN = 70MHz and 75MHz
VDD OVDD 0 –10 CH.1 OUT1A ANALOG 14-BIT S/H –20 INPUT ADC CORE OUT1B –30 –40 CH.2 DATA SERIALIZED 14-BIT OUT2A –50 ANALOG S/H SERIALIZER LVDS ADC CORE INPUT OUT2B OUTPUTS –60 DATA –70 CLOCK ENCODE AMPLITUDE (dBFS) –80 OUT INPUT PLL –90 FRAME –100 –110 GND OGND –120 0 10 20 30 40 50 60 FREQUENCY (MHz) 226814 TA01 226814 TA01b 22687614fa 1 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Digital Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagrams Typical perForMance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts