Datasheet LTC2265-14, LTC2264-14, LTC2263-14 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | 14-Bit, 65Msps Low Power Dual ADCs |
| Páginas / Página | 32 / 9 — TIMING DIAGRAMS. 1-Lane Output Mode, 14-Bit Serialization. 1-Lane Output … |
| Formato / tamaño de archivo | PDF / 1.5 Mb |
| Idioma del documento | Inglés |
TIMING DIAGRAMS. 1-Lane Output Mode, 14-Bit Serialization. 1-Lane Output Mode, 12-Bit Serialization
Línea de modelo para esta hoja de datos
- LTC2263CUJ-14#PBF LTC2263CUJ-14#PBF LTC2263CUJ-14#TRPBF LTC2263CUJ-14#TRPBF LTC2263IUJ-14#PBF LTC2263IUJ-14#PBF LTC2263IUJ-14#TRPBF LTC2263IUJ-14#TRPBF
Versión de texto del documento
LTC2265-14/ LTC2264-14/LTC2263-14
TIMING DIAGRAMS 1-Lane Output Mode, 14-Bit Serialization
tAP N + 1 ANALOG INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D3 D2 D1 D0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D13 D12 D11 D10 OUT#A+ 226514 TD05 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 OUT#B+, OUT#B– ARE DISABLED
1-Lane Output Mode, 12-Bit Serialization
tAP ANALOG N + 1 INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D5 D4 D3 D2 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D13 D12 D11 OUT#A+ 226514 TD06 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 OUT#B+, OUT#B– ARE DISABLED
SPI Port Timing (Readback Mode)
tS tDS tDH tSCK tH CS SCK tDO SDI R/W A6 A5 A4 A3 A2 A1 A0 XX XX XX XX XX XX XX XX SDO D7 D6 D5 D4 D3 D2 D1 D0 HIGH IMPEDANCE
SPI Port Timing (Write Mode)
CS SCK SDI R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDO 226514 TD07 HIGH IMPEDANCE 22654314fb 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
TIMING DIAGRAMS 1-Lane Output Mode, 14-Bit Serialization
tAP N + 1 ANALOG INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D3 D2 D1 D0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D13 D12 D11 D10 OUT#A+ 226514 TD05 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 OUT#B+, OUT#B– ARE DISABLED
1-Lane Output Mode, 12-Bit Serialization
tAP ANALOG N + 1 INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D5 D4 D3 D2 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D13 D12 D11 OUT#A+ 226514 TD06 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 OUT#B+, OUT#B– ARE DISABLED
SPI Port Timing (Readback Mode)
tS tDS tDH tSCK tH CS SCK tDO SDI R/W A6 A5 A4 A3 A2 A1 A0 XX XX XX XX XX XX XX XX SDO D7 D6 D5 D4 D3 D2 D1 D0 HIGH IMPEDANCE
SPI Port Timing (Write Mode)
CS SCK SDI R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDO 226514 TD07 HIGH IMPEDANCE 22654314fb 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts