Datasheet LTC2265-12, LTC2264-12, LTC2263-12 (Analog Devices)
| Fabricante | Analog Devices |
| Descripción | 12-Bit, 65Msps Low Power Dual ADCs |
| Páginas / Página | 34 / 1 — FEATURES. DESCRIPTION. 2-Channel Simultaneous Sampling ADC. 71dB SNR. … |
| Formato / tamaño de archivo | PDF / 1.3 Mb |
| Idioma del documento | Inglés |
FEATURES. DESCRIPTION. 2-Channel Simultaneous Sampling ADC. 71dB SNR. 90dB SFDR. APPLICATIONS. TYPICAL APPLICATION
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LTC2265-12/ LTC2264-12/LTC2263-12 12-Bit, 65Msps/40Msps/ 25Msps Low Power Dual ADCs
FEATURES DESCRIPTION
n
2-Channel Simultaneous Sampling ADC
The LTC®2265-12/LTC2264-12/LTC2263-12 are 2-channel, n
71dB SNR
simultaneous sampling 12-bit A/D converters designed for n
90dB SFDR
digitizing high frequency, wide dynamic range signals. They n Low Power: 167mW/112mW/94mW Total are perfect for demanding communications applications n 83mW/56mW/47mW per Channel with AC performance that includes 71dB SNR and 90dB n Single 1.8V Supply spurious free dynamic range (SFDR). Ultralow jitter of n Serial LVDS Outputs: 1 or 2 Bits per Channel 0.15psRMS allows undersampling of IF frequencies with n Selectable Input Ranges: 1VP-P to 2VP-P excellent noise performance. n 800MHz Full Power Bandwidth S/H DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ) n Shutdown and Nap Modes and no missing codes over temperature. The transition n Serial SPI Port for Configuration noise is a low 0.3LSB n RMS. Pin Compatible 14-Bit and 12-Bit Versions n 40-Pin (6mm × 6mm) QFN Package The digital outputs are serial LVDS to minimize the num- ber of data lines. Each channel outputs two bits at a time (2-lane mode) or one bit at a time (1-lane mode). The LVDS
APPLICATIONS
drivers have optional internal termination and adjustable n output levels to ensure clean signal integrity. Communications n Cellular Base Stations The ENC+ and ENC– inputs may be driven differentially n Software Defined Radios or single-ended with a sine wave, PECL, LVDS, TTL, or n Portable Medical Imaging CMOS inputs. An internal clock duty cycle stabilizer n Multichannel Data Acquisition allows high performance at full speed for a wide range of n Nondestructive Testing clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION LTC2265-12, 65Msps, 2-Tone FFT, fIN = 70MHz and 75MHz
1.8V 1.8V 0 VDD OVDD –10 CH.1 + –20 OUT1A ANALOG S/H 12-BIT –30 INPUT – ADC CORE OUT1B –40 –50 CH.2 + DATA SERIALIZED 12-BIT OUT2A ANALOG S/H SERIALIZER LVDS –60 ADC CORE INPUT – OUT2B OUTPUTS –70 DATA AMPLITUDE (dBFS) –80 CLOCK ENCODE –90 OUT INPUT PLL –100 FRAME –110 –120 GND OGND 0 10 20 30 FREQUENCY (MHz) 226512 TA01 226512 TA02 22654312fb 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
FEATURES DESCRIPTION
n
2-Channel Simultaneous Sampling ADC
The LTC®2265-12/LTC2264-12/LTC2263-12 are 2-channel, n
71dB SNR
simultaneous sampling 12-bit A/D converters designed for n
90dB SFDR
digitizing high frequency, wide dynamic range signals. They n Low Power: 167mW/112mW/94mW Total are perfect for demanding communications applications n 83mW/56mW/47mW per Channel with AC performance that includes 71dB SNR and 90dB n Single 1.8V Supply spurious free dynamic range (SFDR). Ultralow jitter of n Serial LVDS Outputs: 1 or 2 Bits per Channel 0.15psRMS allows undersampling of IF frequencies with n Selectable Input Ranges: 1VP-P to 2VP-P excellent noise performance. n 800MHz Full Power Bandwidth S/H DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ) n Shutdown and Nap Modes and no missing codes over temperature. The transition n Serial SPI Port for Configuration noise is a low 0.3LSB n RMS. Pin Compatible 14-Bit and 12-Bit Versions n 40-Pin (6mm × 6mm) QFN Package The digital outputs are serial LVDS to minimize the num- ber of data lines. Each channel outputs two bits at a time (2-lane mode) or one bit at a time (1-lane mode). The LVDS
APPLICATIONS
drivers have optional internal termination and adjustable n output levels to ensure clean signal integrity. Communications n Cellular Base Stations The ENC+ and ENC– inputs may be driven differentially n Software Defined Radios or single-ended with a sine wave, PECL, LVDS, TTL, or n Portable Medical Imaging CMOS inputs. An internal clock duty cycle stabilizer n Multichannel Data Acquisition allows high performance at full speed for a wide range of n Nondestructive Testing clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION LTC2265-12, 65Msps, 2-Tone FFT, fIN = 70MHz and 75MHz
1.8V 1.8V 0 VDD OVDD –10 CH.1 + –20 OUT1A ANALOG S/H 12-BIT –30 INPUT – ADC CORE OUT1B –40 –50 CH.2 + DATA SERIALIZED 12-BIT OUT2A ANALOG S/H SERIALIZER LVDS –60 ADC CORE INPUT – OUT2B OUTPUTS –70 DATA AMPLITUDE (dBFS) –80 CLOCK ENCODE –90 OUT INPUT PLL –100 FRAME –110 –120 GND OGND 0 10 20 30 FREQUENCY (MHz) 226512 TA01 226512 TA02 22654312fb 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts