Datasheet LTC2262-14 (Analog Devices) - 7

LTC2262-14
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SPI Port Timing (Note 8)
tSCK SCK Period Write Mode l 40 ns Readback Mode, CSDO = 20pF, RPULLUP = 2k l 250 ns tS CS to SCK Setup Time l 5 ns tH SCK to CS Setup Time l 5 ns tDS SDI Setup Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP = 2k l 125 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 5:
VDD = OVDD = 1.8V, fSAMPLE = 150MHz, LVDS outputs with may cause permanent damage to the device. Exposure to any Absolute internal termination disabled, differential ENC+/ENC– = 2VP-P sine wave, Maximum Rating condition for extended periods may affect device input range = 2VP-P with differential drive, unless otherwise noted. reliability and lifetime.
Note 6:
Integral nonlinearity is defined as the deviation of a code from a
Note 2:
All voltage values are with respect to GND with GND and OGND best fit straight line to the transfer curve. The deviation is measured from shorted (unless otherwise noted). the center of the quantization band.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 7:
Offset error is the offset voltage measured from –0.5 LSB when will be clamped by internal diodes. This product can handle input currents the output code flickers between 00 0000 0000 0000 and 11 1111 1111 of greater than 100mA below GND or above VDD without latchup. 1111 in 2’s complement output mode.
Note 4:
When these pin voltages are taken below GND they will be
Note 8:
Guaranteed by design, not subject to test. clamped by internal diodes. When these pin voltages are taken above VDD
Note 9:
VDD = 1.8V, fSAMPLE = 150MHz, ENC+ = single-ended 1.8V square they will not be clamped by internal diodes. This product can handle input wave, ENC– = 0V, input range = 2VP-P with differential drive, 5pF load on currents of greater than 100mA below GND without latchup. each digital output unless otherwise noted.
Note 10:
Recommended operating conditions.
TIMING DIAGRAMS Full-Rate CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels
tAP ANALOG N N + 2 N + 4 INPUT N + 3 tH N + 1 tL ENC– ENC+ tD D0-D13, OF N – 5 N – 4 N – 3 N – 2 N – 1 tC CLKOUT+ CLKOUT– 226214 TD01 226214fc For more information www.linear.com/LTC2262-14 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configurations Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts