Datasheet LTC2261-12, LTC2260-12, LTC2259-12 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | 12-Bit, 125Msps Ultralow Power 1.8V ADCs |
| Páginas / Página | 34 / 8 — TiMing DiagraMs. Double-Data Rate CMOS Output Mode Timing. All Outputs … |
| Formato / tamaño de archivo | PDF / 1.1 Mb |
| Idioma del documento | Inglés |
TiMing DiagraMs. Double-Data Rate CMOS Output Mode Timing. All Outputs Are Single Ended and Have CMOS Levels
Línea de modelo para esta hoja de datos
- LTC2259CUJ-12#PBF LTC2259CUJ-12#PBF LTC2259CUJ-12#TRPBF LTC2259CUJ-12#TRPBF LTC2259IUJ-12#PBF LTC2259IUJ-12#PBF LTC2259IUJ-12#TRPBF LTC2259IUJ-12#TRPBF
Versión de texto del documento
LTC2261-12 LTC2260-12/LTC2259-12
TiMing DiagraMs Double-Data Rate CMOS Output Mode Timing All Outputs Are Single Ended and Have CMOS Levels
tAP ANALOG N N + 2 N + 4 INPUT N + 3 tH N + 1 tL ENC– ENC+ tD tD D0_1 D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 D0N-2 D1N-2 ••• D10_11 D10N-5 D11N-5 D10N-4 D11N-4 D10N-3 D11N-3 D10N-2 D11N-2 OF OFN-5 OFN-4 OFN-3 OFN-2 tC tC CLKOUT+ CLKOUT– 226112 TD02
Double-Data Rate LVDS Output Mode Timing All Outputs Are Differential and Have LVDS Levels
tAP ANALOG N N + 2 N + 4 INPUT N + 3 tH N + 1 tL ENC– ENC+ tD tD D0_1+ D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 D0N-2 D1N-2 D0_1– ••• D10_11+ D10N-5 D11N-5 D10N-4 D11N-4 D10N-3 D11N-3 D10N-2 D11N-2 D10_11– OF+ OFN-5 OFN-4 OFN-3 OFN-3 OF– tC tC CLKOUT+ CLKOUT– 226112 TD03 226112fc 8 For more information www.linear.com/LTC2261-12 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configurations Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
TiMing DiagraMs Double-Data Rate CMOS Output Mode Timing All Outputs Are Single Ended and Have CMOS Levels
tAP ANALOG N N + 2 N + 4 INPUT N + 3 tH N + 1 tL ENC– ENC+ tD tD D0_1 D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 D0N-2 D1N-2 ••• D10_11 D10N-5 D11N-5 D10N-4 D11N-4 D10N-3 D11N-3 D10N-2 D11N-2 OF OFN-5 OFN-4 OFN-3 OFN-2 tC tC CLKOUT+ CLKOUT– 226112 TD02
Double-Data Rate LVDS Output Mode Timing All Outputs Are Differential and Have LVDS Levels
tAP ANALOG N N + 2 N + 4 INPUT N + 3 tH N + 1 tL ENC– ENC+ tD tD D0_1+ D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 D0N-2 D1N-2 D0_1– ••• D10_11+ D10N-5 D11N-5 D10N-4 D11N-4 D10N-3 D11N-3 D10N-2 D11N-2 D10_11– OF+ OFN-5 OFN-4 OFN-3 OFN-3 OF– tC tC CLKOUT+ CLKOUT– 226112 TD03 226112fc 8 For more information www.linear.com/LTC2261-12 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configurations Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts