Datasheet LTC2261-12, LTC2260-12, LTC2259-12 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | 12-Bit, 125Msps Ultralow Power 1.8V ADCs |
| Páginas / Página | 34 / 6 — p ower requireMenTs The. denotes the specifications which apply over the … |
| Formato / tamaño de archivo | PDF / 1.1 Mb |
| Idioma del documento | Inglés |
p ower requireMenTs The. denotes the specifications which apply over the full operating temperature
Línea de modelo para esta hoja de datos
- LTC2259CUJ-12#PBF LTC2259CUJ-12#PBF LTC2259CUJ-12#TRPBF LTC2259CUJ-12#TRPBF LTC2259IUJ-12#PBF LTC2259IUJ-12#PBF LTC2259IUJ-12#TRPBF LTC2259IUJ-12#TRPBF
Versión de texto del documento
LTC2261-12 LTC2260-12/LTC2259-12
p ower requireMenTs The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTC2261-12 LTC2260-12 LTC2259-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS CMOS Output Modes: Full-Data Rate and Double-Data Rate
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.1 1.9 1.1 1.9 1.1 1.9 V IVDD Analog Supply Current DC Input l 68.7 81.1 57.1 67.4 48 56.6 mA Sine Wave Input 70 58.3 49 mA IOVDD Digital Supply Current Sine Wave Input, OVDD=1.2V 3.5 2.9 2.2 mA PDISS Power Dissipation DC Input l 124 146 103 122 87 102 mW Sine Wave Input, OVDD=1.2V 130 108 91 mW
LVDS Output Mode
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.9 1.7 1.9 1.7 1.9 V IVDD Analog Supply Current Sine Wave Input l 73.6 86.9 61.9 73.1 52.7 62.2 mA IOVDD Digital Supply Current Sine Input, 1.75mA Mode l 18.8 22.2 18.8 22.2 18.8 22.2 mA (0VDD = 1.8V) Sine Input, 3.5mA Mode l 36.7 43.3 36.7 43.3 36.7 43.3 mA PDISS Power Dissipation Sine Input, 1.75mA Mode l 166 196 145 172 129 152 mW Sine Input, 3.5mA Mode l 199 235 177 210 161 190 mW
All Output Modes
PSLEEP Sleep Mode Power 0.5 0.5 0.5 mW PNAP Nap Mode Power 9 9 9 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 10 10 10 mW (No Increase for Nap or Sleep Modes)
Ti Ming characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2261-12 LTC2260-12 LTC2259-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS Sampling Frequency (Note 10) l 1 125 1 105 1 80 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 500 4.52 4.76 500 5.93 6.25 500 ns Duty Cycle Stabilizer On l 2.0 4 500 2.00 4.76 500 2.00 6.25 500 ns tH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 500 4.52 4.76 500 5.93 6.25 500 ns Duty Cycle Stabilizer On l 2.0 4 500 2.00 4.76 500 2.00 6.25 500 ns tAP Sample-and-Hold 0 0 0 ns Acquisition Delay Time
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (CMOS Modes: Full-Data Rate and Double-Data Rate)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.7 3.1 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.4 2.6 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency Full-Data Rate Mode 5.0 Cycles Double-Data Rate Mode 5.5 Cycles 226112fc 6 For more information www.linear.com/LTC2261-12 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configurations Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
p ower requireMenTs The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTC2261-12 LTC2260-12 LTC2259-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS CMOS Output Modes: Full-Data Rate and Double-Data Rate
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.1 1.9 1.1 1.9 1.1 1.9 V IVDD Analog Supply Current DC Input l 68.7 81.1 57.1 67.4 48 56.6 mA Sine Wave Input 70 58.3 49 mA IOVDD Digital Supply Current Sine Wave Input, OVDD=1.2V 3.5 2.9 2.2 mA PDISS Power Dissipation DC Input l 124 146 103 122 87 102 mW Sine Wave Input, OVDD=1.2V 130 108 91 mW
LVDS Output Mode
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.9 1.7 1.9 1.7 1.9 V IVDD Analog Supply Current Sine Wave Input l 73.6 86.9 61.9 73.1 52.7 62.2 mA IOVDD Digital Supply Current Sine Input, 1.75mA Mode l 18.8 22.2 18.8 22.2 18.8 22.2 mA (0VDD = 1.8V) Sine Input, 3.5mA Mode l 36.7 43.3 36.7 43.3 36.7 43.3 mA PDISS Power Dissipation Sine Input, 1.75mA Mode l 166 196 145 172 129 152 mW Sine Input, 3.5mA Mode l 199 235 177 210 161 190 mW
All Output Modes
PSLEEP Sleep Mode Power 0.5 0.5 0.5 mW PNAP Nap Mode Power 9 9 9 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 10 10 10 mW (No Increase for Nap or Sleep Modes)
Ti Ming characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2261-12 LTC2260-12 LTC2259-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS Sampling Frequency (Note 10) l 1 125 1 105 1 80 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 500 4.52 4.76 500 5.93 6.25 500 ns Duty Cycle Stabilizer On l 2.0 4 500 2.00 4.76 500 2.00 6.25 500 ns tH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 500 4.52 4.76 500 5.93 6.25 500 ns Duty Cycle Stabilizer On l 2.0 4 500 2.00 4.76 500 2.00 6.25 500 ns tAP Sample-and-Hold 0 0 0 ns Acquisition Delay Time
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (CMOS Modes: Full-Data Rate and Double-Data Rate)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.7 3.1 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.4 2.6 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency Full-Data Rate Mode 5.0 Cycles Double-Data Rate Mode 5.5 Cycles 226112fc 6 For more information www.linear.com/LTC2261-12 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configurations Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts