Datasheet LTC2246H (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | 14-Bit, 25Msps 125°C ADC In LQFP |
| Páginas / Página | 18 / 7 — PIN FUNCTIONS. GND (Pins 1, 4, 9, 13, 15, 18, 24, 25, 29, 32, 36, 37,. OE … |
| Formato / tamaño de archivo | PDF / 205 Kb |
| Idioma del documento | Inglés |
PIN FUNCTIONS. GND (Pins 1, 4, 9, 13, 15, 18, 24, 25, 29, 32, 36, 37,. OE (Pin 17):. 48):. A +. IN (Pin 2):
Línea de modelo para esta hoja de datos
Versión de texto del documento
LTC2246H
PIN FUNCTIONS GND (Pins 1, 4, 9, 13, 15, 18, 24, 25, 29, 32, 36, 37, OE (Pin 17):
Output Enable Pin. Refer to SHDN pin
48):
ADC Power Ground. function.
A + IN (Pin 2):
Positive Differential Analog Input.
D0-D13 (Pins 19-23, 26-28, 33-35, 38-40):
Digital Out- puts. D13 is the MSB.
A – IN (Pin 3):
Negative Differential Analog Input.
OGND (Pin 30):
Output Driver Ground.
REFH (Pins 5, 6):
ADC High Reference. Bypass to Pins 7, 8 with a 0.1μF ceramic chip capacitor as close to the pin
OVDD (Pin 31):
Positive Supply for the Output Drivers. as possible. Also bypass to Pins 7, 8 with an additional Bypass to ground with 0.1μF ceramic chip capacitor. 2.2μF ceramic chip capacitor and to ground with a 1μF
OF (Pin 41):
Over/Under Flow Output. High when an over ceramic chip capacitor. or under fl ow has occurred.
REFL (Pins 7, 8):
ADC Low Reference. Bypass to Pins 5, 6
MODE (Pin 42):
Output Format and Clock Duty Cycle with a 0.1μF ceramic chip capacitor as close to the pin Stabilizer Selection Pin. Connecting MODE to GND selects as possible. Also bypass to Pins 5, 6 with an additional offset binary output format and turns the clock duty cycle 2.2μF ceramic chip capacitor and to ground with a 1μF stabilizer off. 1/3 V ceramic chip capacitor. DD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects
VDD (Pins 10, 11, 12, 46, 47):
3V Supply. Bypass to GND 2’s complement output format and turns the clock duty with 0.1μF ceramic chip capacitors. cycle stabilizer on. VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off.
CLK (Pin 14):
Clock Input. The input sample starts on the positive edge.
SENSE (Pin 43):
Reference Programming Pin. Connecting SENSE to V
SHDN (Pin 16):
Shutdown Mode Selection Pin. Connecting CM selects the internal reference and a ±0.5V input range. V SHDN to GND and OE to GND results in normal operation DD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and with the outputs enabled. Connecting SHDN to GND and OE less than 1V applied to SENSE selects an input range of to VDD results in normal operation with the outputs at ±V high impedance. Connecting SHDN to V SENSE. ±1V is the largest valid input range. DD and OE to GND results in nap mode with the outputs at high impedance.
VCM (Pin 44, 45):
1.5V Output and Input Common Connecting SHDN to VDD and OE to VDD results in sleep Mode Bias. Bypass to ground with 2.2μF ceramic chip mode with the outputs at high impedance. capacitor. If the clock duty cycle stabilizer is used, a >1μs high pulse should be applied to the SHDN pin once the power supplies are stable at power up. 2246hfb 7
PIN FUNCTIONS GND (Pins 1, 4, 9, 13, 15, 18, 24, 25, 29, 32, 36, 37, OE (Pin 17):
Output Enable Pin. Refer to SHDN pin
48):
ADC Power Ground. function.
A + IN (Pin 2):
Positive Differential Analog Input.
D0-D13 (Pins 19-23, 26-28, 33-35, 38-40):
Digital Out- puts. D13 is the MSB.
A – IN (Pin 3):
Negative Differential Analog Input.
OGND (Pin 30):
Output Driver Ground.
REFH (Pins 5, 6):
ADC High Reference. Bypass to Pins 7, 8 with a 0.1μF ceramic chip capacitor as close to the pin
OVDD (Pin 31):
Positive Supply for the Output Drivers. as possible. Also bypass to Pins 7, 8 with an additional Bypass to ground with 0.1μF ceramic chip capacitor. 2.2μF ceramic chip capacitor and to ground with a 1μF
OF (Pin 41):
Over/Under Flow Output. High when an over ceramic chip capacitor. or under fl ow has occurred.
REFL (Pins 7, 8):
ADC Low Reference. Bypass to Pins 5, 6
MODE (Pin 42):
Output Format and Clock Duty Cycle with a 0.1μF ceramic chip capacitor as close to the pin Stabilizer Selection Pin. Connecting MODE to GND selects as possible. Also bypass to Pins 5, 6 with an additional offset binary output format and turns the clock duty cycle 2.2μF ceramic chip capacitor and to ground with a 1μF stabilizer off. 1/3 V ceramic chip capacitor. DD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects
VDD (Pins 10, 11, 12, 46, 47):
3V Supply. Bypass to GND 2’s complement output format and turns the clock duty with 0.1μF ceramic chip capacitors. cycle stabilizer on. VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off.
CLK (Pin 14):
Clock Input. The input sample starts on the positive edge.
SENSE (Pin 43):
Reference Programming Pin. Connecting SENSE to V
SHDN (Pin 16):
Shutdown Mode Selection Pin. Connecting CM selects the internal reference and a ±0.5V input range. V SHDN to GND and OE to GND results in normal operation DD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and with the outputs enabled. Connecting SHDN to GND and OE less than 1V applied to SENSE selects an input range of to VDD results in normal operation with the outputs at ±V high impedance. Connecting SHDN to V SENSE. ±1V is the largest valid input range. DD and OE to GND results in nap mode with the outputs at high impedance.
VCM (Pin 44, 45):
1.5V Output and Input Common Connecting SHDN to VDD and OE to VDD results in sleep Mode Bias. Bypass to ground with 2.2μF ceramic chip mode with the outputs at high impedance. capacitor. If the clock duty cycle stabilizer is used, a >1μs high pulse should be applied to the SHDN pin once the power supplies are stable at power up. 2246hfb 7