Datasheet LTC2245 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | 14-Bit, 10Msps Low Power 3V ADC |
| Páginas / Página | 20 / 7 — TYPICAL PERFOR A CE CHARACTERISTICS. VDD vs Sample Rate,. OVDD vs Sample … |
| Formato / tamaño de archivo | PDF / 528 Kb |
| Idioma del documento | Inglés |
TYPICAL PERFOR A CE CHARACTERISTICS. VDD vs Sample Rate,. OVDD vs Sample Rate, 5MHz Sine. 5MHz Sine Wave Input, –1dB
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LTC2245
W U TYPICAL PERFOR A CE CHARACTERISTICS I I VDD vs Sample Rate, OVDD vs Sample Rate, 5MHz Sine 5MHz Sine Wave Input, –1dB Wave Input, –1dB, OVDD = 1.8V
25 1.0 0.9 2V RANGE 0.8 0.7 20 0.6 1V RANGE (mA) (mA) 0.5 I VDD I OVDD 0.4 15 0.3 0.2 0.1 10 0 0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14 SAMPLE RATE (Msps) SAMPLE RATE (Msps) 2245 G12 2245 G13
U U U PI FU CTIO S AIN+ (Pin 1):
Positive Differential Analog Input. outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high
AIN- (Pin 2):
Negative Differential Analog Input. impedance. Connecting SHDN to VDD and OE to VDD
REFH (Pins 3, 4):
ADC High Reference. Short together and results in sleep mode with the outputs at high impedance. bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as
OE (Pin 11):
Output Enable Pin. Refer to SHDN pin close to the pin as possible. Also bypass to pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground function. with a 1µF ceramic chip capacitor.
D0 – D13 (Pins 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24, REFL (Pins 5, 6):
ADC Low Reference. Short together and
25, 26, 27):
Digital Outputs. D13 is the MSB. bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as
OGND (Pin 20):
Output Driver Ground. close to the pin as possible. Also bypass to pins 3, 4 with an additional 2.2µF ceramic chip capacitor and to ground
OVDD (Pin 21):
Positive Supply for the Output Drivers. with a 1µF ceramic chip capacitor. Bypass to ground with 0.1µF ceramic chip capacitor.
V OF (Pin 28):
Over/Under Flow Output. High when an over
DD (Pins 7, 32):
3V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. or under flow has occurred.
GND (Pin 8):
ADC Power Ground.
MODE (Pin 29):
Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to GND selects
CLK (Pin 9):
Clock Input. The input sample starts on the offset binary output format and turns the clock duty cycle positive edge. stabilizer off. 1/3 VDD selects offset binary output format
SHDN (Pin 10):
Shutdown Mode Selection Pin. Connect- and turns the clock duty cycle stabilizer on. 2/3 VDD selects ing SHDN to GND and OE to GND results in normal 2’s complement output format and turns the clock duty operation with the outputs enabled. Connecting SHDN to cycle stabilizer on. VDD selects 2’s complement output GND and OE to VDD results in normal operation with the format and turns the clock duty cycle stabilizer off. 2245fa 7
W U TYPICAL PERFOR A CE CHARACTERISTICS I I VDD vs Sample Rate, OVDD vs Sample Rate, 5MHz Sine 5MHz Sine Wave Input, –1dB Wave Input, –1dB, OVDD = 1.8V
25 1.0 0.9 2V RANGE 0.8 0.7 20 0.6 1V RANGE (mA) (mA) 0.5 I VDD I OVDD 0.4 15 0.3 0.2 0.1 10 0 0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14 SAMPLE RATE (Msps) SAMPLE RATE (Msps) 2245 G12 2245 G13
U U U PI FU CTIO S AIN+ (Pin 1):
Positive Differential Analog Input. outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high
AIN- (Pin 2):
Negative Differential Analog Input. impedance. Connecting SHDN to VDD and OE to VDD
REFH (Pins 3, 4):
ADC High Reference. Short together and results in sleep mode with the outputs at high impedance. bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as
OE (Pin 11):
Output Enable Pin. Refer to SHDN pin close to the pin as possible. Also bypass to pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground function. with a 1µF ceramic chip capacitor.
D0 – D13 (Pins 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24, REFL (Pins 5, 6):
ADC Low Reference. Short together and
25, 26, 27):
Digital Outputs. D13 is the MSB. bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as
OGND (Pin 20):
Output Driver Ground. close to the pin as possible. Also bypass to pins 3, 4 with an additional 2.2µF ceramic chip capacitor and to ground
OVDD (Pin 21):
Positive Supply for the Output Drivers. with a 1µF ceramic chip capacitor. Bypass to ground with 0.1µF ceramic chip capacitor.
V OF (Pin 28):
Over/Under Flow Output. High when an over
DD (Pins 7, 32):
3V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. or under flow has occurred.
GND (Pin 8):
ADC Power Ground.
MODE (Pin 29):
Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to GND selects
CLK (Pin 9):
Clock Input. The input sample starts on the offset binary output format and turns the clock duty cycle positive edge. stabilizer off. 1/3 VDD selects offset binary output format
SHDN (Pin 10):
Shutdown Mode Selection Pin. Connect- and turns the clock duty cycle stabilizer on. 2/3 VDD selects ing SHDN to GND and OE to GND results in normal 2’s complement output format and turns the clock duty operation with the outputs enabled. Connecting SHDN to cycle stabilizer on. VDD selects 2’s complement output GND and OE to VDD results in normal operation with the format and turns the clock duty cycle stabilizer off. 2245fa 7