Datasheet LTC2222, LTC2223 (Analog Devices)
| Fabricante | Analog Devices |
| Descripción | 12-Bit, 80Msps ADCs |
| Páginas / Página | 28 / 1 — FEATURES. DESCRIPTION. Sample Rate: 105Msps/80Msps. 68dB SNR up to 140MHz … |
| Formato / tamaño de archivo | PDF / 946 Kb |
| Idioma del documento | Inglés |
FEATURES. DESCRIPTION. Sample Rate: 105Msps/80Msps. 68dB SNR up to 140MHz Input. 80dB SFDR up to 170MHz Input
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LTC2222/LTC2223 12-Bit,105Msps/ 80Msps ADCs
FEATURES DESCRIPTION
n
Sample Rate: 105Msps/80Msps
The LTC®2222 and LTC2223 are 105Msps/80Msps, sam- n
68dB SNR up to 140MHz Input
pling 12-bit A/D converters designed for digitizing high n
80dB SFDR up to 170MHz Input
frequency, wide dynamic range signals. The LTC2222/ n
775MHz Full Power Bandwidth S/H
LTC2223 are perfect for demanding communications n
Single 3.3V Supply
applications with AC performance that includes 68dB n
Low Power Dissipation: 475mW/366mW
SNR and 80dB spurious free dynamic range for signals n Selectable Input Ranges: ±0.5V or ±1V up to 170MHz. Ultralow jitter of 0.15psRMS allows n No Missing Codes undersampling of IF frequencies with excellent noise n Optional Clock Duty Cycle Stabilizer performance. n Shutdown and Nap Modes DC specs include ±0.3LSB INL (typ), ±0.2LSB DNL (typ) n Data Ready Output Clock and no missing codes over temperature. The transition n Pin Compatible Family noise is a low 0.5LSBRMS. 135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit) 105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit) A separate output power supply allows the outputs to 80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit) drive 0.5V to 3.6V logic. n 48-Pin QFN Package The ENC+ and ENC– inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL, or
APPLICATIONS
CMOS inputs. An optional clock duty cycle stabilizer al- lows high performance at full speed for a wide range of n Wireless and Wired Broadband Communication clock duty cycles. n Cable Head-End Systems L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n Power Amplifi er Linearization Technology Corporation. All other trademarks are the property of their respective owners. n Communications Test Equipment
TYPICAL APPLICATION
VDD 3.3V
SFDR vs Input Frequency
100 REFH FLEXIBLE 95 REFL REFERENCE 4th OR HIGHER 0VDD 90 0.5V TO 3.6V 85 + D11 12-BIT • ANALOG INPUT CORRECTION OUTPUT PIPELINED 80 • INPUT S/H LOGIC DRIVERS ADC CORE • 2nd or 3rd – SFDR (dBFS) D0 75 70 0GND 65 CLOCK/DUTY CYCLE 60 CONTROL 0 100 200 300 400 500 600 INPUT FREQUENCY (MHz) 22223 TA01b 22223 TA01 ENCODE INPUT 22223fb 1
FEATURES DESCRIPTION
n
Sample Rate: 105Msps/80Msps
The LTC®2222 and LTC2223 are 105Msps/80Msps, sam- n
68dB SNR up to 140MHz Input
pling 12-bit A/D converters designed for digitizing high n
80dB SFDR up to 170MHz Input
frequency, wide dynamic range signals. The LTC2222/ n
775MHz Full Power Bandwidth S/H
LTC2223 are perfect for demanding communications n
Single 3.3V Supply
applications with AC performance that includes 68dB n
Low Power Dissipation: 475mW/366mW
SNR and 80dB spurious free dynamic range for signals n Selectable Input Ranges: ±0.5V or ±1V up to 170MHz. Ultralow jitter of 0.15psRMS allows n No Missing Codes undersampling of IF frequencies with excellent noise n Optional Clock Duty Cycle Stabilizer performance. n Shutdown and Nap Modes DC specs include ±0.3LSB INL (typ), ±0.2LSB DNL (typ) n Data Ready Output Clock and no missing codes over temperature. The transition n Pin Compatible Family noise is a low 0.5LSBRMS. 135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit) 105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit) A separate output power supply allows the outputs to 80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit) drive 0.5V to 3.6V logic. n 48-Pin QFN Package The ENC+ and ENC– inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL, or
APPLICATIONS
CMOS inputs. An optional clock duty cycle stabilizer al- lows high performance at full speed for a wide range of n Wireless and Wired Broadband Communication clock duty cycles. n Cable Head-End Systems L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n Power Amplifi er Linearization Technology Corporation. All other trademarks are the property of their respective owners. n Communications Test Equipment
TYPICAL APPLICATION
VDD 3.3V
SFDR vs Input Frequency
100 REFH FLEXIBLE 95 REFL REFERENCE 4th OR HIGHER 0VDD 90 0.5V TO 3.6V 85 + D11 12-BIT • ANALOG INPUT CORRECTION OUTPUT PIPELINED 80 • INPUT S/H LOGIC DRIVERS ADC CORE • 2nd or 3rd – SFDR (dBFS) D0 75 70 0GND 65 CLOCK/DUTY CYCLE 60 CONTROL 0 100 200 300 400 500 600 INPUT FREQUENCY (MHz) 22223 TA01b 22223 TA01 ENCODE INPUT 22223fb 1