Datasheet LTC2205, LTC2204 (Analog Devices)
| Fabricante | Analog Devices |
| Descripción | 16-Bit, 65Msps ADCs |
| Páginas / Página | 36 / 1 — FEATURES. DESCRIPTION. Sample Rate: 65Msps/40Msps. 79dB SNR and 100dB … |
| Formato / tamaño de archivo | PDF / 1.4 Mb |
| Idioma del documento | Inglés |
FEATURES. DESCRIPTION. Sample Rate: 65Msps/40Msps. 79dB SNR and 100dB SFDR (2.25VP-P Range)
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LTC2205/LTC2204 16-Bit, 65Msps/40Msps ADCs
FEATURES DESCRIPTION
n
Sample Rate: 65Msps/40Msps
The LTC®2205/LTC2204 are sampling 16-bit A/D converters n
79dB SNR and 100dB SFDR (2.25VP-P Range)
designed for digitizing high frequency, wide dynamic range n
SFDR >92dB at 140MHz (1.5VP-P Input Range)
signals up to input frequencies of 700MHz. The input range n
PGA Front End (2.25VP-P or 1.5VP-P Input Range)
of the ADC can be optimized with the PGA front end. n
700MHz Full Power Bandwidth S/H
The LTC2205/LTC2204 are perfect for demanding n
Optional Internal Dither
communications applications, with AC performance that n
Optional Data Output Randomizer
includes 79dB SNR and 100dB spurious free dynamic range n Single 3.3V Supply (SFDR). Ultralow jitter of 90fsRMS allows undersampling of n Power Dissipation: 610mW/480mW high input frequencies with excellent noise performance. n Optional Clock Duty Cycle Stabilizer Maximum DC specs include ±4LSB INL, ±1LSB DNL (no n Out-of-Range Indicator missing codes). n Pin Compatible Family 105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit) A separate output power supply allows the CMOS output 80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit) swing to range from 0.5V to 3.6V. 65Msps: LTC2205 (16-Bit), LTC2205-14 (14-Bit) The ENC+ and ENC– inputs may be driven differentially 40Msps: LTC2204 (16-Bit) or single-ended with a sine wave, PECL, LVDS, TTL or n 48-Pin (7mm × 7mm) QFN Package CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock
APPLICATIONS
duty cycles. n Telecommunications , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n Receivers n Cellular Base Stations n Spectrum Analysis n Imaging Systems n ATE
TYPICAL APPLICATION
3.3V
LTC2205: 64K Point FFT,
SENSE
fIN = 5.1MHz, –1dBFS,
OV 1.25V INTERNAL ADC DD V
PGA = 0, DITH = 0
CM 0.5V TO 3.6V COMMON MODE REFERENCE 2.2μF BIAS VOLTAGE GENERATOR 0.1μF 0 OF –20 AIN+ + CLKOUT 16-BIT CORRECTION OUTPUT D15 –40 ANALOG S/H PIPELINED LOGIC AND DRIVERS • INPUT AMP ADC CORE SHIFT REGISTER –60 – • AIN– • D0 –80 OGND AMPLITUDE (dBFS) –100 CLOCK/DUTY CYCLE V 3.3V DD –120 CONTROL 0.1μF 0.1μF 0.1μF GND 22076 TA01 –140 0 5 10 15 20 25 30 ENC ENC PGA SHDN DITH MODE OE RAND FREQUENCY (MHz) 22054 TA01b ADC CONTROL INPUTS 22054fc 1
FEATURES DESCRIPTION
n
Sample Rate: 65Msps/40Msps
The LTC®2205/LTC2204 are sampling 16-bit A/D converters n
79dB SNR and 100dB SFDR (2.25VP-P Range)
designed for digitizing high frequency, wide dynamic range n
SFDR >92dB at 140MHz (1.5VP-P Input Range)
signals up to input frequencies of 700MHz. The input range n
PGA Front End (2.25VP-P or 1.5VP-P Input Range)
of the ADC can be optimized with the PGA front end. n
700MHz Full Power Bandwidth S/H
The LTC2205/LTC2204 are perfect for demanding n
Optional Internal Dither
communications applications, with AC performance that n
Optional Data Output Randomizer
includes 79dB SNR and 100dB spurious free dynamic range n Single 3.3V Supply (SFDR). Ultralow jitter of 90fsRMS allows undersampling of n Power Dissipation: 610mW/480mW high input frequencies with excellent noise performance. n Optional Clock Duty Cycle Stabilizer Maximum DC specs include ±4LSB INL, ±1LSB DNL (no n Out-of-Range Indicator missing codes). n Pin Compatible Family 105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit) A separate output power supply allows the CMOS output 80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit) swing to range from 0.5V to 3.6V. 65Msps: LTC2205 (16-Bit), LTC2205-14 (14-Bit) The ENC+ and ENC– inputs may be driven differentially 40Msps: LTC2204 (16-Bit) or single-ended with a sine wave, PECL, LVDS, TTL or n 48-Pin (7mm × 7mm) QFN Package CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock
APPLICATIONS
duty cycles. n Telecommunications , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n Receivers n Cellular Base Stations n Spectrum Analysis n Imaging Systems n ATE
TYPICAL APPLICATION
3.3V
LTC2205: 64K Point FFT,
SENSE
fIN = 5.1MHz, –1dBFS,
OV 1.25V INTERNAL ADC DD V
PGA = 0, DITH = 0
CM 0.5V TO 3.6V COMMON MODE REFERENCE 2.2μF BIAS VOLTAGE GENERATOR 0.1μF 0 OF –20 AIN+ + CLKOUT 16-BIT CORRECTION OUTPUT D15 –40 ANALOG S/H PIPELINED LOGIC AND DRIVERS • INPUT AMP ADC CORE SHIFT REGISTER –60 – • AIN– • D0 –80 OGND AMPLITUDE (dBFS) –100 CLOCK/DUTY CYCLE V 3.3V DD –120 CONTROL 0.1μF 0.1μF 0.1μF GND 22076 TA01 –140 0 5 10 15 20 25 30 ENC ENC PGA SHDN DITH MODE OE RAND FREQUENCY (MHz) 22054 TA01b ADC CONTROL INPUTS 22054fc 1