Datasheet LTC2185, LTC2184, LTC2183 (Analog Devices)
| Fabricante | Analog Devices |
| Descripción | 16-Bit, 125Msps Low Power Dual ADCs |
| Páginas / Página | 36 / 1 — FeaTures. DescripTion. applicaTions. Typical applicaTion. 2-Tone FFT, fIN … |
| Formato / tamaño de archivo | PDF / 824 Kb |
| Idioma del documento | Inglés |
FeaTures. DescripTion. applicaTions. Typical applicaTion. 2-Tone FFT, fIN = 70MHz and 69MHz
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Versión de texto del documento
LTC2185/LTC2184/LTC2183 16-Bit, 125/105/80Msps Low Power Dual ADCs
FeaTures DescripTion
n Two-Channel Simultaneously Sampling ADC The LTC®2185/LTC2184/LTC2183 are two-channel si- n 76.8dB SNR multaneous sampling 16-bit A/D converters designed for n 90dB SFDR digitizing high frequency, wide dynamic range signals. n Low Power: 370mW/308mW/200mW Total They are perfect for demanding communications applica- 185mW/154mW/100mW per Channel tions with AC performance that includes 76.8dB SNR and n Single 1.8V Supply 90dB spurious free dynamic range (SFDR). Ultralow jitter n CMOS, DDR CMOS, or DDR LVDS Outputs of 0.07psRMS allows undersampling of IF frequencies with n Selectable Input Ranges: 1VP-P to 2VP-P excellent noise performance. n 550MHz Full Power Bandwidth S/H DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) n Optional Data Output Randomizer and no missing codes over temperature. The transition n Optional Clock Duty Cycle Stabilizer noise is 3.4LSBRMS. n Shutdown and Nap Modes n Serial SPI Port for Configuration The digital outputs can be either full rate CMOS, Double n 64-Pin (9mm × 9mm) QFN Package Data Rate CMOS, or Double Data Rate LVDS. A separate output power supply allows the CMOS output swing to
applicaTions
range from 1.2V to 1.8V. The ENC+ and ENC– inputs may be driven differentially n Communications or single-ended with a sine wave, PECL, LVDS, TTL, or n Cellular Base Stations CMOS inputs. An optional clock duty cycle stabilizer al- n Software Defined Radios lows high performance at full speed for a wide range of n Portable Medical Imaging clock duty cycles. n Multi-Channel Data Acquisition L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n Nondestructive Testing Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
1.8V 1.8V
2-Tone FFT, fIN = 70MHz and 69MHz
VDD OVDD 0 –10 –20 CH 1 D1_15 ANALOG S/H 16-BIT –30 ADC CORE • INPUT • –40 • CMOS, D1_0 –50 DDR CMOS OR DDR LVDS –60 D2_15 OUTPUTS –70 OUTPUT • CH 2 DRIVERS • AMPLITUDE (dBFS) –80 ANALOG S/H 16-BIT • D2_0 –90 INPUT ADC CORE –100 –110 –120 125MHz CLOCK 0 10 20 30 40 50 60 CONTROL CLOCK FREQUENCY (MHz) 218543 TA01b 218543 TA01a GND OGND 218543f 1 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts
FeaTures DescripTion
n Two-Channel Simultaneously Sampling ADC The LTC®2185/LTC2184/LTC2183 are two-channel si- n 76.8dB SNR multaneous sampling 16-bit A/D converters designed for n 90dB SFDR digitizing high frequency, wide dynamic range signals. n Low Power: 370mW/308mW/200mW Total They are perfect for demanding communications applica- 185mW/154mW/100mW per Channel tions with AC performance that includes 76.8dB SNR and n Single 1.8V Supply 90dB spurious free dynamic range (SFDR). Ultralow jitter n CMOS, DDR CMOS, or DDR LVDS Outputs of 0.07psRMS allows undersampling of IF frequencies with n Selectable Input Ranges: 1VP-P to 2VP-P excellent noise performance. n 550MHz Full Power Bandwidth S/H DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) n Optional Data Output Randomizer and no missing codes over temperature. The transition n Optional Clock Duty Cycle Stabilizer noise is 3.4LSBRMS. n Shutdown and Nap Modes n Serial SPI Port for Configuration The digital outputs can be either full rate CMOS, Double n 64-Pin (9mm × 9mm) QFN Package Data Rate CMOS, or Double Data Rate LVDS. A separate output power supply allows the CMOS output swing to
applicaTions
range from 1.2V to 1.8V. The ENC+ and ENC– inputs may be driven differentially n Communications or single-ended with a sine wave, PECL, LVDS, TTL, or n Cellular Base Stations CMOS inputs. An optional clock duty cycle stabilizer al- n Software Defined Radios lows high performance at full speed for a wide range of n Portable Medical Imaging clock duty cycles. n Multi-Channel Data Acquisition L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n Nondestructive Testing Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
1.8V 1.8V
2-Tone FFT, fIN = 70MHz and 69MHz
VDD OVDD 0 –10 –20 CH 1 D1_15 ANALOG S/H 16-BIT –30 ADC CORE • INPUT • –40 • CMOS, D1_0 –50 DDR CMOS OR DDR LVDS –60 D2_15 OUTPUTS –70 OUTPUT • CH 2 DRIVERS • AMPLITUDE (dBFS) –80 ANALOG S/H 16-BIT • D2_0 –90 INPUT ADC CORE –100 –110 –120 125MHz CLOCK 0 10 20 30 40 50 60 CONTROL CLOCK FREQUENCY (MHz) 218543 TA01b 218543 TA01a GND OGND 218543f 1 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts