Datasheet LTC2175-14, LTC2174-14, LTC2173-14 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | 14-Bit, 125Msps Low Power Quad ADCs |
| Páginas / Página | 34 / 8 — TiMing DiagraMs. 2-Lane Output Mode, 16-Bit Serialization*. 2-Lane Output … |
| Formato / tamaño de archivo | PDF / 873 Kb |
| Idioma del documento | Inglés |
TiMing DiagraMs. 2-Lane Output Mode, 16-Bit Serialization*. 2-Lane Output Mode, 14-Bit Serialization
Línea de modelo para esta hoja de datos
- LTC2173CUKG-14#PBF LTC2173CUKG-14#PBF LTC2173CUKG-14#TRPBF LTC2173CUKG-14#TRPBF LTC2173IUKG-14#PBF LTC2173IUKG-14#PBF LTC2173IUKG-14#TRPBF LTC2173IUKG-14#TRPBF
Versión de texto del documento
LTC2175-14/ LTC2174-14/LTC2173-14
TiMing DiagraMs 2-Lane Output Mode, 16-Bit Serialization*
tAP N+1 ANALOG N INPUT tENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D5 D3 D1 0 D13 D11 D9 D7 D5 D3 D1 0 D13 D11 D9 OUT#A+ OUT#B– D4 D2 D0 0 D12 D10 D8 D6 D4 D2 D0 0 D12 D10 D8 OUT#B+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 217514 TD01 *SEE THE DIGITAL OUTPUTS SECTION
2-Lane Output Mode, 14-Bit Serialization
tAP ANALOG N+2 N INPUT t N+1 ENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 OUT#A+ OUT#B– D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 OUT#B+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 SAMPLE N-3 217514 TD02 NOTE THAT IN THIS MODE FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC– 21754314fa 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
TiMing DiagraMs 2-Lane Output Mode, 16-Bit Serialization*
tAP N+1 ANALOG N INPUT tENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D5 D3 D1 0 D13 D11 D9 D7 D5 D3 D1 0 D13 D11 D9 OUT#A+ OUT#B– D4 D2 D0 0 D12 D10 D8 D6 D4 D2 D0 0 D12 D10 D8 OUT#B+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 217514 TD01 *SEE THE DIGITAL OUTPUTS SECTION
2-Lane Output Mode, 14-Bit Serialization
tAP ANALOG N+2 N INPUT t N+1 ENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 OUT#A+ OUT#B– D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 OUT#B+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 SAMPLE N-3 217514 TD02 NOTE THAT IN THIS MODE FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC– 21754314fa 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts