Datasheet LTC2172-14, LTC2171-14, LTC2170-14 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | 14-Bit, 65Msps Low Power Quad ADCs |
| Páginas / Página | 34 / 8 — TiMing DiagraMs. 2-Lane Output Mode, 16-Bit Serialization*. 2-Lane Output … |
| Formato / tamaño de archivo | PDF / 1.6 Mb |
| Idioma del documento | Inglés |
TiMing DiagraMs. 2-Lane Output Mode, 16-Bit Serialization*. 2-Lane Output Mode, 14-Bit Serialization
Línea de modelo para esta hoja de datos
- LTC2170CUKG-14#PBF LTC2170CUKG-14#PBF LTC2170CUKG-14#TRPBF LTC2170CUKG-14#TRPBF LTC2170IUKG-14#PBF LTC2170IUKG-14#PBF LTC2170IUKG-14#TRPBF LTC2170IUKG-14#TRPBF
Versión de texto del documento
LTC2172-14/ LTC2171-14/LTC2170-14
TiMing DiagraMs 2-Lane Output Mode, 16-Bit Serialization*
tAP N + 1 ANALOG INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ t t DATA tSER FRAME FR– FR+ tPD tSER OUT#A– D5 D3 D1 0 D13 D11 D9 D7 D5 D3 D1 0 D13 D11 D9 OUT#A+ OUT#B– D4 D2 D0 0 D12 D10 D8 D6 D4 D2 D0 0 D12 D10 D8 OUT#B+ 217214 TD01 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 *SEE THE DIGITAL OUTPUTS SECTION
2-Lane Output Mode, 14-Bit Serialization
tAP ANALOG N + 2 N + 1 INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ t t DATA tSER FRAME FR– FR+ tPD tSER OUT#A– D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 OUT#A+ OUT#B– D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 OUT#B+ 217214 TD02 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 SAMPLE N-3 NOTE THAT IN THIS MODE, FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC– 21721014fb 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
TiMing DiagraMs 2-Lane Output Mode, 16-Bit Serialization*
tAP N + 1 ANALOG INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ t t DATA tSER FRAME FR– FR+ tPD tSER OUT#A– D5 D3 D1 0 D13 D11 D9 D7 D5 D3 D1 0 D13 D11 D9 OUT#A+ OUT#B– D4 D2 D0 0 D12 D10 D8 D6 D4 D2 D0 0 D12 D10 D8 OUT#B+ 217214 TD01 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 *SEE THE DIGITAL OUTPUTS SECTION
2-Lane Output Mode, 14-Bit Serialization
tAP ANALOG N + 2 N + 1 INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ t t DATA tSER FRAME FR– FR+ tPD tSER OUT#A– D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 OUT#A+ OUT#B– D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 OUT#B+ 217214 TD02 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 SAMPLE N-3 NOTE THAT IN THIS MODE, FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC– 21721014fb 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts