Datasheet LTC2159 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | 16-Bit, 20Msps Low Power ADC |
| Páginas / Página | 32 / 7 — power requireMenTs. The. denotes the specifications which apply over the … |
| Formato / tamaño de archivo | PDF / 532 Kb |
| Idioma del documento | Inglés |
power requireMenTs. The. denotes the specifications which apply over the full operating temperature
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LTC2159
power requireMenTs The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS All Output Modes
PSLEEP Sleep Mode Power 1 mW PNAP Nap Mode Power 10 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 20 mW (No Increase for Nap or Sleep Modes)
TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 10) l 1 20 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 20 25 500 ns Duty Cycle Stabilizer On l 2 25 500 ns tH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 20 25 500 ns Duty Cycle Stabilizer On l 2 25 500 ns tAP Sample-and-Hold Acquisition Delay Time 0 ns
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.7 3.1 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.4 2.6 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency Full Data Rate Mode 6 Cycles Double Data Rate Mode 6.5 Cycles
DIGITAL DATA OUTPUTS (LVDS MODE)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.8 3.2 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.5 2.7 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency 6.5 Cycles
SPI PORT TIMING (Note 8)
tSCK SCK Period Write Mode l 40 ns Readback Mode, CSDO = 20pF, RPULLUP = 2k l 250 ns tS CS to SCK Setup Time l 5 ns tH SCK to CS Setup Time l 5 ns tDS SDI Setup Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP = 2k l 125 ns 2159f 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts
power requireMenTs The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS All Output Modes
PSLEEP Sleep Mode Power 1 mW PNAP Nap Mode Power 10 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 20 mW (No Increase for Nap or Sleep Modes)
TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 10) l 1 20 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 20 25 500 ns Duty Cycle Stabilizer On l 2 25 500 ns tH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 20 25 500 ns Duty Cycle Stabilizer On l 2 25 500 ns tAP Sample-and-Hold Acquisition Delay Time 0 ns
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.7 3.1 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.4 2.6 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency Full Data Rate Mode 6 Cycles Double Data Rate Mode 6.5 Cycles
DIGITAL DATA OUTPUTS (LVDS MODE)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.8 3.2 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.5 2.7 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency 6.5 Cycles
SPI PORT TIMING (Note 8)
tSCK SCK Period Write Mode l 40 ns Readback Mode, CSDO = 20pF, RPULLUP = 2k l 250 ns tS CS to SCK Setup Time l 5 ns tH SCK to CS Setup Time l 5 ns tDS SDI Setup Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP = 2k l 125 ns 2159f 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts