Datasheet LTC2157-12, LTC2156-12, LTC2155-12 (Analog Devices)
| Fabricante | Analog Devices |
| Descripción | Dual 12-Bit 250Msps ADCs |
| Páginas / Página | 32 / 1 — FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. LTC2157-12: 32K … |
| Formato / tamaño de archivo | PDF / 946 Kb |
| Idioma del documento | Inglés |
FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. LTC2157-12: 32K Points 2-Tone FFT,. fIN = 71MHZ and 69MHz, 250Msps
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Versión de texto del documento
LTC2157-12/ LTC2156-12/LTC2155-12 Dual 12-Bit 250Msps/ 210Msps/170Msps ADCs
FEATURES DESCRIPTION
n 68.5dB SNR The LTC®2157-12/LTC2156-12/LTC2155-12 are a family of n 90dB SFDR dual 250Msps/210Msps/170Msps 12-bit A/D converters n Low Power: 628mW/592mW/545mW Total designed for digitizing high frequency, wide dynamic range n Single 1.8V Supply signals. They are perfect for demanding communications n DDR LVDS Outputs applications with AC performance that includes 68.5dB n Easy-to-Drive 1.5VP-P Input Range SNR and 90dB spurious free dynamic range (SFDR). The n 1.25GHz Full-Power Bandwidth S/H 1.25GHz input bandwidth allows the ADC to achieve high n Optional Clock Duty Cycle Stabilizer undersampling ratio with very low attenuation. The latency n Low Power Sleep and Nap Modes is only six clock cycles. n Serial SPI Port for Configuration DC specs include ±0.26LSB INL (typ), ±0.16LSB DNL (typ) n Pin Compatible 14-Bit Versions and no missing codes over temperature. The transition n 64-Lead (9mm × 9mm) QFN Package noise is 0.54LSBRMS.
APPLICATIONS
The digital outputs are double data rate (DDR) LVDS. The ENC+ and ENC– inputs can be driven differentially with n Communications a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional n Cellular Basestations clock duty cycle stabilizer allows high performance at full n Software Defined Radios speed for a wide range of clock duty cycles. n Medical Imaging L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n High Definition Video Technology Corporation. All other trademarks are the property of their respective owners. n Testing and Measurement Instruments
TYPICAL APPLICATION
VDD OV
LTC2157-12: 32K Points 2-Tone FFT,
DD CHANNEL A
fIN = 71MHZ and 69MHz, 250Msps
DA10_11 0 12-BIT ANALOG CORRECTION • S/H OUTPUT PIPELINED DDR INPUT LOGIC DRIVERS • ADC CORE LVDS • –20 DA0_1 –40 CLOCK/DUTY OGND CLOCK CYCLE –60 CONTROL OVDD CHANNEL B AMPLITUDE (dBFS) –80 DB10_11 –100 12-BIT • ANALOG CORRECTION S/H OUTPUT PIPELINED • DDR INPUT LOGIC DRIVERS ADC CORE • LVDS –120 DB0_1 0 20 40 60 80 100 120 FREQUENCY (MHz) GND 21576512 G11 21576512 TA01 OGND 21576512fb For more information www.linear.com/LTC2157-12 1 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs And Outputs Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Related Parts
FEATURES DESCRIPTION
n 68.5dB SNR The LTC®2157-12/LTC2156-12/LTC2155-12 are a family of n 90dB SFDR dual 250Msps/210Msps/170Msps 12-bit A/D converters n Low Power: 628mW/592mW/545mW Total designed for digitizing high frequency, wide dynamic range n Single 1.8V Supply signals. They are perfect for demanding communications n DDR LVDS Outputs applications with AC performance that includes 68.5dB n Easy-to-Drive 1.5VP-P Input Range SNR and 90dB spurious free dynamic range (SFDR). The n 1.25GHz Full-Power Bandwidth S/H 1.25GHz input bandwidth allows the ADC to achieve high n Optional Clock Duty Cycle Stabilizer undersampling ratio with very low attenuation. The latency n Low Power Sleep and Nap Modes is only six clock cycles. n Serial SPI Port for Configuration DC specs include ±0.26LSB INL (typ), ±0.16LSB DNL (typ) n Pin Compatible 14-Bit Versions and no missing codes over temperature. The transition n 64-Lead (9mm × 9mm) QFN Package noise is 0.54LSBRMS.
APPLICATIONS
The digital outputs are double data rate (DDR) LVDS. The ENC+ and ENC– inputs can be driven differentially with n Communications a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional n Cellular Basestations clock duty cycle stabilizer allows high performance at full n Software Defined Radios speed for a wide range of clock duty cycles. n Medical Imaging L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n High Definition Video Technology Corporation. All other trademarks are the property of their respective owners. n Testing and Measurement Instruments
TYPICAL APPLICATION
VDD OV
LTC2157-12: 32K Points 2-Tone FFT,
DD CHANNEL A
fIN = 71MHZ and 69MHz, 250Msps
DA10_11 0 12-BIT ANALOG CORRECTION • S/H OUTPUT PIPELINED DDR INPUT LOGIC DRIVERS • ADC CORE LVDS • –20 DA0_1 –40 CLOCK/DUTY OGND CLOCK CYCLE –60 CONTROL OVDD CHANNEL B AMPLITUDE (dBFS) –80 DB10_11 –100 12-BIT • ANALOG CORRECTION S/H OUTPUT PIPELINED • DDR INPUT LOGIC DRIVERS ADC CORE • LVDS –120 DB0_1 0 20 40 60 80 100 120 FREQUENCY (MHz) GND 21576512 G11 21576512 TA01 OGND 21576512fb For more information www.linear.com/LTC2157-12 1 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs And Outputs Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Related Parts