Datasheet LTC2153-14 (Analog Devices) - 9

LTC2153-14
pin FuncTions OGND (Pin 21):
LVDS Driver Ground.
PAR/SER (Pin 40):
Programming Mode Selection Pin.
SDO (Pin 36):
Serial Interface Data Output. In serial pro- Connect to ground to enable the serial programming gramming mode, (PAR/SER = 0V), SDO is the optional serial mode. CS, SCK, SDI and SDO become a serial interface interface data output. Data on SDO is read back from the that control the A/D operating modes. Connect to VDD to mode control registers and can be latched on the falling enable the parallel programming mode where CS, SCK and edge of SCK. SDO is an open-drain N-channel MOSFET SDI become parallel logic inputs that control a reduced output that requires an external 2k pull-up resistor from set of the A/D operating modes. PAR/SER should be con- 1.8V to 3.3V. If readback from the mode control registers nected directly to ground or the VDD of the part and not is not needed, the pull-up resistor is not necessary and be driven by a logic signal. SDO can be left unconnected.
LVDS Outputs (DDR LVDS) SDI (Pin 37):
Serial Interface Data Input. In serial program- The following pins are differential LVDS outputs. The ming mode, (PAR/SER = 0V), SDI is the serial interface output current level is programmable. There is an optional data input. Data on SDI is clocked into the mode control internal 100Ω termination resistor between the pins of registers on the rising edge of SCK. In parallel programming each LVDS output pair. mode (PAR/SER = VDD), SDI selects 3.5mA or 1.75mA
D –/D + to D –/D + (Pins 16/17, 18/19,
LVDS output current (see Table 2).
0_1 0_1 12_13 12_13 22/23, 24/25, 28/29, 31/32, 33/34):
Double-Data Rate
SCK (Pin 38):
Serial Interface Clock Input. In serial Digital Outputs. Two data bits are multiplexed onto each programming mode, (PAR/SER = 0V), SCK is the serial differential output pair. The even data bits (D0, D2, D4, interface clock input. In parallel programming mode (PAR/ D6, D8, D10, D12) appear when CLKOUT+ is low. The odd SER = VDD), SCK controls the sleep mode (see Table 2). data bits (D1, D3, D5, D7, D9, D11, D13) appear when
CS (Pin 39):
Serial Interface Chip Select Input. In serial CLKOUT+ is high. programming mode, (PAR/SER = 0V), CS is the serial in-
CLKOUT–, CLKOUT+ (Pins 26, 27):
Data Output Clock. terface chip select input. When CS is low, SCK is enabled The digital outputs normally transition at the same time for shifting data on SDI into the mode control registers. In as the falling and rising edges of CLKOUT+. The phase of parallel programming mode (PAR/SER = VDD), CS controls CLKOUT+ can also be delayed relative to the digital outputs the clock duty cycle stabilizer (see Table 2). by programming the mode control registers.
OF–, OF+ (Pins 14, 15):
Over/Underflow Digital Output. OF+ is high when an overflow or underflow has occurred. This underflow is valid only when CLKOUT+ is low. In the second half clock cycle, the overflow is set to 0. 215314fa For more information www.linear.com/LTC2153-14 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs And Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagrams Applications Information Package Description Related Parts