Datasheet LTC2123 (Analog Devices)
| Fabricante | Analog Devices |
| Descripción | Dual 14-Bit 250Msps ADC with JESD204B Serial Outputs |
| Páginas / Página | 50 / 1 — FEATURES. DESCRIPTION. 5Gbps JESD204B Interface. APPLICATIONS. TYPICAL … |
| Formato / tamaño de archivo | PDF / 1.2 Mb |
| Idioma del documento | Inglés |
FEATURES. DESCRIPTION. 5Gbps JESD204B Interface. APPLICATIONS. TYPICAL APPLICATION. 64k Point 2-Tone FFT,. IN = 71.1MHz and 69MHz,
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LTC2123 Dual 14-Bit 250Msps ADC with JESD204B Serial Outputs
FEATURES DESCRIPTION
n
5Gbps JESD204B Interface
The LTC®2123 is a 2-channel simultaneous sampling n 70dBFS SNR 250Msps 14-bit A/D converter with serial JESD204B n 90dBFS SFDR outputs. It is designed for digitizing high frequency, n Low Power: 864mW Total wide dynamic range signals. It is perfect for demanding n Single 1.8V Supply communications applications with AC performance that n Easy to Drive 1.5VP-P Input Range includes 70dBFS SNR and 90dBFS spurious free dynamic n 1.25GHz Full Power Bandwidth S/H range (SFDR). The 1.25GHz input bandwidth allows the n Optional Clock Divide by Two ADC to under-sample high frequencies. n Optional Clock Duty Cycle Stabilizer The 5Gbps JESD204B serial interface simplifies the PCB n Low Power Sleep and Nap Modes design by minimizing the number of data lines required. n Serial SPI Port for Configuration n 48-Lead (7mm × 7mm) QFN Package The DEVCLK+ and DEVCLK– inputs can be driven differ- entially with sine wave, PECL, or LVDS signals. An optional clock divide-by-two circuit or clock duty cycle stabilizer
APPLICATIONS
maintains high performance at full speed for a wide range n of clock duty cycles. Communications n Cellular Base Stations L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n Software Defined Radios n Medical Imaging n High Definition Video n Test and Measurement Instrumentation
TYPICAL APPLICATION
OVDD
64k Point 2-Tone FFT,
1.2V TO 1.9V
f
LTC2123
IN = 71.1MHz and 69MHz,
50Ω 50Ω
–7dBFS, 250Msps
0 ANALOG JESD204B 14-BIT ADC SERIALIZER 5Gbps INPUT LOGIC –20 –40 –60 CLOCK JESD204B CLOCK PLL ÷ 2 OR ÷ 1 OVDD FPGA OR ASIC 1.2V TO 1.9V –80 AMPLITUDE (dBFS) (250MHz OR 500MHz) 50Ω 50Ω –100 –120 ANALOG JESD204B 14-BIT ADC SERIALIZER 5Gbps 0 20 40 60 80 100 120 INPUT LOGIC FREQUENCY (MHz) 2123 TA01b 2123 TA01a 2123fc For more information www.linear.com/LTC2123 1 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Converter Characteristics Pin Configuration Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs and Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram SPI Timing Definitions Applications Information Typical Applications Package Description Typical Application Related Parts
FEATURES DESCRIPTION
n
5Gbps JESD204B Interface
The LTC®2123 is a 2-channel simultaneous sampling n 70dBFS SNR 250Msps 14-bit A/D converter with serial JESD204B n 90dBFS SFDR outputs. It is designed for digitizing high frequency, n Low Power: 864mW Total wide dynamic range signals. It is perfect for demanding n Single 1.8V Supply communications applications with AC performance that n Easy to Drive 1.5VP-P Input Range includes 70dBFS SNR and 90dBFS spurious free dynamic n 1.25GHz Full Power Bandwidth S/H range (SFDR). The 1.25GHz input bandwidth allows the n Optional Clock Divide by Two ADC to under-sample high frequencies. n Optional Clock Duty Cycle Stabilizer The 5Gbps JESD204B serial interface simplifies the PCB n Low Power Sleep and Nap Modes design by minimizing the number of data lines required. n Serial SPI Port for Configuration n 48-Lead (7mm × 7mm) QFN Package The DEVCLK+ and DEVCLK– inputs can be driven differ- entially with sine wave, PECL, or LVDS signals. An optional clock divide-by-two circuit or clock duty cycle stabilizer
APPLICATIONS
maintains high performance at full speed for a wide range n of clock duty cycles. Communications n Cellular Base Stations L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n Software Defined Radios n Medical Imaging n High Definition Video n Test and Measurement Instrumentation
TYPICAL APPLICATION
OVDD
64k Point 2-Tone FFT,
1.2V TO 1.9V
f
LTC2123
IN = 71.1MHz and 69MHz,
50Ω 50Ω
–7dBFS, 250Msps
0 ANALOG JESD204B 14-BIT ADC SERIALIZER 5Gbps INPUT LOGIC –20 –40 –60 CLOCK JESD204B CLOCK PLL ÷ 2 OR ÷ 1 OVDD FPGA OR ASIC 1.2V TO 1.9V –80 AMPLITUDE (dBFS) (250MHz OR 500MHz) 50Ω 50Ω –100 –120 ANALOG JESD204B 14-BIT ADC SERIALIZER 5Gbps 0 20 40 60 80 100 120 INPUT LOGIC FREQUENCY (MHz) 2123 TA01b 2123 TA01a 2123fc For more information www.linear.com/LTC2123 1 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Converter Characteristics Pin Configuration Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs and Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram SPI Timing Definitions Applications Information Typical Applications Package Description Typical Application Related Parts