Datasheet LTC2122 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | Dual14-Bit 170Msps ADC with JESD204B Serial Outputs |
| Páginas / Página | 50 / 6 — TIMING CHARACTERISTICS. The. denotes the specifications which apply over … |
| Formato / tamaño de archivo | PDF / 1.5 Mb |
| Idioma del documento | Inglés |
TIMING CHARACTERISTICS. The. denotes the specifications which apply over the full operating temperature
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LTC2122
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tDS SDI to SCK Rising Set Up Time l 5 ns tDH SCK Rising to SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Readback Mode CSDO = 20pF, RPULLUP = 2kΩ l 125 ns
JESD204B Timing (Note 8)
tBIT, UI High Speed Serial Bit Period 1 Lane Mode (2 ADC to One Lane) l 167 1000 ps 2 Lane Mode (1 Lane Per ADC) l 294 1000 ps tJIT Total Jitter of CML Outputs (P-P) > 3.125Gbps Per Lane (BER = 1E-15, Note 8) l 0.3 UI ≤ 3.125Gbps Per Lane (BER = 1E-12, Note 8) l 0.35 UI tSU_SYN SYNC~ to CLK Set-Up Time (Note 8) l 0.6 ns tH_SYN DEVCLK to SYNC~ Hold Time (Note 8) l 0.6 ns tSU_SYS SYSREF to DEVCLK Set-Up Time (Note 8) l 0.2 (tDCK – 0.32) ns tH_SYS DEVCLK to SYSREF Hold Time (Note 8) l 0.32 ns LATP1 Pipeline Latency, Single-Lane Mode (Note 10) l 10.5 10.5 tS LATP2 Pipeline Latency, 2-Lane Mode (Note 10) l 13.5 13.5 tS tDS Delay from DEVCLK to Serial Data Out (Note 8) l 0.6 tS LATSC1 Latency from SYNC~ Assertion to COMMA (Note 10) l 7 7 tS Out, Single Lane Mode LATSC2 Latency from SYNC~ Assertion to COMMA (Note 10) l 10 10 tS Out, 2-Lane Mode LATSL1 Latency from SYNC~ De-assertion to LAS (Note 10, 11) l 3 3 tS Out, Single-Lane Mode LATSL2 Latency from SYNC~ De-assertion to LAS (Note 10, 11) l 6 6 tS Out, 2-Lane Mode LATOF Overflow Latency (Note 10) l 6 6 tS tD_OF1X Analog Delay of OF with 1X_CLK (Note 8) l 1.4 1.7 2.0 ns tD_OF2X Analog Delay of OF with 2X_CLK (Note 8) l 1.6 1.9 2.2 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 6:
Integral nonlinearity is defined as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute best fit straight line to the transfer curve. The deviation is measured from Maximum Rating condition for extended periods may affect device the center of the quantization band. reliability and lifetime.
Note 7:
Offset error is the offset voltage measured from –0.5LSB when the
Note 2:
All voltage values are with respect to GND (unless otherwise noted). output code flickers between 01 1111 1111 1111 and 10 0000 0000 0000.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 8:
Guaranteed by design, not subject to test. will be clamped by internal diodes. This product can handle input currents
Note 9:
Recommended operating conditions. of greater than 100mA below GND or above VDD without latchup.
Note 10:
When the “2×_CLK” SPI register bit is set, the DEVCLK
Note 4:
When these pin voltages are taken below GND they will be frequency is 2× the sampling frequency. When the “2×_CLK” bit is not clamped by internal diodes. When these pin voltages are taken above VDD they will not be clamped by internal diodes. This product can handle input set, the DEVCLK frequency is equal to the sampling frequency. Latency is currents of greater than 100mA below GND without latchup. measured in units of sampling periods (tS), where tS is the inverse of the sampling frequency.
Note 5:
VDD = 1.8V, fSAMPLE = 170MHz, differential DEVCLK+/DEVCLK– = 2V
Note 11:
When in subclass 0, the Lane Alignment Sequence (LAS) latency P-P sine wave, input range = 1.5VP-P with differential drive, unless otherwise noted. measurement begins at the start of the frame following the detection of SYNC~ de-assertion. When in subclasses 1 or 2 this LAS latency measurement begins at the start of the first multiframe following the detection of SYNC~ de-assertion. 2122fb 6 For more information www.linear.com/LTC2122 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs And Outputs Digital Inputs And Outputs Timing characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram SPI Timing Definitions ADC PERFORMANCE TERMS SERIAL INTERFACE TERMS Applications Information CONVERTER OPERATION INPUT DRIVE CIRCUITS GROUNDING AND BYPASSING HEAT TRANSFER Typical Applications Package Description Revision History Typical Application Related Parts
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tDS SDI to SCK Rising Set Up Time l 5 ns tDH SCK Rising to SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Readback Mode CSDO = 20pF, RPULLUP = 2kΩ l 125 ns
JESD204B Timing (Note 8)
tBIT, UI High Speed Serial Bit Period 1 Lane Mode (2 ADC to One Lane) l 167 1000 ps 2 Lane Mode (1 Lane Per ADC) l 294 1000 ps tJIT Total Jitter of CML Outputs (P-P) > 3.125Gbps Per Lane (BER = 1E-15, Note 8) l 0.3 UI ≤ 3.125Gbps Per Lane (BER = 1E-12, Note 8) l 0.35 UI tSU_SYN SYNC~ to CLK Set-Up Time (Note 8) l 0.6 ns tH_SYN DEVCLK to SYNC~ Hold Time (Note 8) l 0.6 ns tSU_SYS SYSREF to DEVCLK Set-Up Time (Note 8) l 0.2 (tDCK – 0.32) ns tH_SYS DEVCLK to SYSREF Hold Time (Note 8) l 0.32 ns LATP1 Pipeline Latency, Single-Lane Mode (Note 10) l 10.5 10.5 tS LATP2 Pipeline Latency, 2-Lane Mode (Note 10) l 13.5 13.5 tS tDS Delay from DEVCLK to Serial Data Out (Note 8) l 0.6 tS LATSC1 Latency from SYNC~ Assertion to COMMA (Note 10) l 7 7 tS Out, Single Lane Mode LATSC2 Latency from SYNC~ Assertion to COMMA (Note 10) l 10 10 tS Out, 2-Lane Mode LATSL1 Latency from SYNC~ De-assertion to LAS (Note 10, 11) l 3 3 tS Out, Single-Lane Mode LATSL2 Latency from SYNC~ De-assertion to LAS (Note 10, 11) l 6 6 tS Out, 2-Lane Mode LATOF Overflow Latency (Note 10) l 6 6 tS tD_OF1X Analog Delay of OF with 1X_CLK (Note 8) l 1.4 1.7 2.0 ns tD_OF2X Analog Delay of OF with 2X_CLK (Note 8) l 1.6 1.9 2.2 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 6:
Integral nonlinearity is defined as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute best fit straight line to the transfer curve. The deviation is measured from Maximum Rating condition for extended periods may affect device the center of the quantization band. reliability and lifetime.
Note 7:
Offset error is the offset voltage measured from –0.5LSB when the
Note 2:
All voltage values are with respect to GND (unless otherwise noted). output code flickers between 01 1111 1111 1111 and 10 0000 0000 0000.
Note 3:
When these pin voltages are taken below GND or above VDD, they
Note 8:
Guaranteed by design, not subject to test. will be clamped by internal diodes. This product can handle input currents
Note 9:
Recommended operating conditions. of greater than 100mA below GND or above VDD without latchup.
Note 10:
When the “2×_CLK” SPI register bit is set, the DEVCLK
Note 4:
When these pin voltages are taken below GND they will be frequency is 2× the sampling frequency. When the “2×_CLK” bit is not clamped by internal diodes. When these pin voltages are taken above VDD they will not be clamped by internal diodes. This product can handle input set, the DEVCLK frequency is equal to the sampling frequency. Latency is currents of greater than 100mA below GND without latchup. measured in units of sampling periods (tS), where tS is the inverse of the sampling frequency.
Note 5:
VDD = 1.8V, fSAMPLE = 170MHz, differential DEVCLK+/DEVCLK– = 2V
Note 11:
When in subclass 0, the Lane Alignment Sequence (LAS) latency P-P sine wave, input range = 1.5VP-P with differential drive, unless otherwise noted. measurement begins at the start of the frame following the detection of SYNC~ de-assertion. When in subclasses 1 or 2 this LAS latency measurement begins at the start of the first multiframe following the detection of SYNC~ de-assertion. 2122fb 6 For more information www.linear.com/LTC2122 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs And Outputs Digital Inputs And Outputs Timing characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram SPI Timing Definitions ADC PERFORMANCE TERMS SERIAL INTERFACE TERMS Applications Information CONVERTER OPERATION INPUT DRIVE CIRCUITS GROUNDING AND BYPASSING HEAT TRANSFER Typical Applications Package Description Revision History Typical Application Related Parts