Datasheet LTC1864L, LTC1865L (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | µPower, 3V, 16-Bit, 150ksps 1- and 2-Channel ADCs in MSOP |
| Páginas / Página | 16 / 9 — APPLICATIO S I FOR ATIO. LTC1864L OPERATION. Analog Inputs. Operating … |
| Formato / tamaño de archivo | PDF / 366 Kb |
| Idioma del documento | Inglés |
APPLICATIO S I FOR ATIO. LTC1864L OPERATION. Analog Inputs. Operating Sequence. Reference Input
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- LTC1864LACMS8#PBF LTC1864LACMS8#PBF LTC1864LACMS8#TRPBF LTC1864LACMS8#TRPBF LTC1864LACS8#PBF LTC1864LACS8#PBF LTC1864LACS8#TRPBF LTC1864LACS8#TRPBF LTC1864LAIMS8#PBF LTC1864LAIMS8#PBF LTC1864LAIMS8#TRPBF LTC1864LAIMS8#TRPBF LTC1864LAIS8#PBF LTC1864LAIS8#PBF LTC1864LAIS8#TRPBF LTC1864LAIS8#TRPBF LTC1864LCMS8#PBF LTC1864LCMS8#PBF LTC1864LCMS8#TRPBF LTC1864LCMS8#TRPBF LTC1864LCS8#PBF LTC1864LCS8#PBF LTC1864LCS8#TRPBF LTC1864LCS8#TRPBF LTC1864LIMS8#PBF LTC1864LIMS8#PBF LTC1864LIMS8#TRPBF LTC1864LIMS8#TRPBF LTC1864LIS8#PBF LTC1864LIS8#PBF LTC1864LIS8#TRPBF LTC1864LIS8#TRPBF
- LTC1865LACMS#PBF LTC1865LACMS#PBF LTC1865LACMS#TRPBF LTC1865LACMS#TRPBF LTC1865LACS8#PBF LTC1865LACS8#PBF LTC1865LACS8#TRPBF LTC1865LACS8#TRPBF LTC1865LAIMS#PBF LTC1865LAIMS#PBF LTC1865LAIMS#TRPBF LTC1865LAIMS#TRPBF LTC1865LAIS8#PBF LTC1865LAIS8#PBF LTC1865LAIS8#TRPBF LTC1865LAIS8#TRPBF LTC1865LCMS#PBF LTC1865LCMS#PBF LTC1865LCMS#TRPBF LTC1865LCMS#TRPBF LTC1865LCS8#PBF LTC1865LCS8#PBF LTC1865LCS8#TRPBF LTC1865LCS8#TRPBF LTC1865LIMS#PBF LTC1865LIMS#PBF LTC1865LIMS#TRPBF LTC1865LIMS#TRPBF LTC1865LIS8#PBF LTC1865LIS8#PBF LTC1865LIS8#TRPBF LTC1865LIS8#TRPBF
Versión de texto del documento
LTC1864L/LTC1865L
U U W U APPLICATIO S I FOR ATIO LTC1864L OPERATION Analog Inputs
The LTC1864L has a unipolar differential analog input. The
Operating Sequence
converter will measure the voltage between the “IN+” and The LTC1864L conversion cycle begins with the rising “IN–” inputs. A zero code will occur when IN+ minus IN– edge of CONV. After a period equal to tCONV, the conver- equals zero. Full scale occurs when IN+ minus IN– equals sion is finished. If CONV is left high after this time, the VREF minus 1LSB. See Figure 2. Both the “IN+” and LTC1864L goes into sleep mode drawing only leakage “IN–” inputs are sampled at the same time, so common current. On the falling edge of CONV, the LTC1864L goes mode noise on the inputs is rejected by the ADC. If “IN–” into sample mode and SDO is enabled. SCK synchronizes is grounded and VREF is tied to VCC, a rail-to-rail input span the data transfer with each bit being transmitted from SDO will result on “IN+” as shown in Figure 3. on the falling SCK edge. The receiving system should capture the data from SDO on the rising edge of SCK. After
Reference Input
completing the data transfer, if further SCK clocks are The voltage on the reference input of the LTC1864L applied with CONV low, SDO will output zeros indefinitely. defines the full-scale range of the A/D converter. The See Figure 1. LTC1864L can operate with reference voltages from VCC to 1V. CONV tSMPL tCONV SLEEP MODE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK DON'T CARE SDO B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* Hi-Z Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY 1854 F01
Figure 1. LTC1864L Operating Sequence
1µF VCC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 LTC1864L • 1 8 • VREF VCC • 2 7 VIN = 0V TO VCC IN+ SCK 3 6 SERIAL DATA LINK TO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 VIN* IN– SDO ASIC, PLD, MPU, DSP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 5 OR SHIFT REGISTERS 0V 1LSB V V V GND CONV REF REF REF 1864 F03 *VIN = IN+ – IN– – 2LSB – 1LSB 1864 F02
Figure 2. LTC1864L Transfer Curve Figure 3. LTC1864L with Rail-to-Rail Input Span
sn18645L 18645Lfs 9
U U W U APPLICATIO S I FOR ATIO LTC1864L OPERATION Analog Inputs
The LTC1864L has a unipolar differential analog input. The
Operating Sequence
converter will measure the voltage between the “IN+” and The LTC1864L conversion cycle begins with the rising “IN–” inputs. A zero code will occur when IN+ minus IN– edge of CONV. After a period equal to tCONV, the conver- equals zero. Full scale occurs when IN+ minus IN– equals sion is finished. If CONV is left high after this time, the VREF minus 1LSB. See Figure 2. Both the “IN+” and LTC1864L goes into sleep mode drawing only leakage “IN–” inputs are sampled at the same time, so common current. On the falling edge of CONV, the LTC1864L goes mode noise on the inputs is rejected by the ADC. If “IN–” into sample mode and SDO is enabled. SCK synchronizes is grounded and VREF is tied to VCC, a rail-to-rail input span the data transfer with each bit being transmitted from SDO will result on “IN+” as shown in Figure 3. on the falling SCK edge. The receiving system should capture the data from SDO on the rising edge of SCK. After
Reference Input
completing the data transfer, if further SCK clocks are The voltage on the reference input of the LTC1864L applied with CONV low, SDO will output zeros indefinitely. defines the full-scale range of the A/D converter. The See Figure 1. LTC1864L can operate with reference voltages from VCC to 1V. CONV tSMPL tCONV SLEEP MODE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK DON'T CARE SDO B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* Hi-Z Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY 1854 F01
Figure 1. LTC1864L Operating Sequence
1µF VCC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 LTC1864L • 1 8 • VREF VCC • 2 7 VIN = 0V TO VCC IN+ SCK 3 6 SERIAL DATA LINK TO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 VIN* IN– SDO ASIC, PLD, MPU, DSP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 5 OR SHIFT REGISTERS 0V 1LSB V V V GND CONV REF REF REF 1864 F03 *VIN = IN+ – IN– – 2LSB – 1LSB 1864 F02
Figure 2. LTC1864L Transfer Curve Figure 3. LTC1864L with Rail-to-Rail Input Span
sn18645L 18645Lfs 9