Datasheet LTC1860, LTC1861 (Analog Devices) - 10
| Fabricante | Analog Devices |
| Descripción | µPower, 12-Bit, 250ksps 1- and 2-Channel ADCs in MSOP |
| Páginas / Página | 18 / 10 — FuncTional block DiagraM. TesT circuiTs. Load Circuit for tdDO, tr, tf, … |
| Formato / tamaño de archivo | PDF / 377 Kb |
| Idioma del documento | Inglés |
FuncTional block DiagraM. TesT circuiTs. Load Circuit for tdDO, tr, tf, tdis and ten
Línea de modelo para esta hoja de datos
- LTC1860CMS8#PBF LTC1860CMS8#PBF LTC1860CMS8#TRPBF LTC1860CMS8#TRPBF LTC1860CS8#PBF LTC1860CS8#PBF LTC1860CS8#TRPBF LTC1860CS8#TRPBF LTC1860HMS8#PBF LTC1860HMS8#PBF LTC1860HMS8#TRPBF LTC1860HMS8#TRPBF LTC1860IMS8#PBF LTC1860IMS8#PBF LTC1860IMS8#TRPBF LTC1860IMS8#TRPBF LTC1860IS8#PBF LTC1860IS8#PBF LTC1860IS8#TRPBF LTC1860IS8#TRPBF
- LTC1861CMS#PBF LTC1861CMS#PBF LTC1861CMS#TRPBF LTC1861CMS#TRPBF LTC1861CS8#PBF LTC1861CS8#PBF LTC1861CS8#TRPBF LTC1861CS8#TRPBF LTC1861HMS#PBF LTC1861HMS#PBF LTC1861HMS#TRPBF LTC1861HMS#TRPBF LTC1861IMS#PBF LTC1861IMS#PBF LTC1861IMS#TRPBF LTC1861IMS#TRPBF LTC1861IS8#PBF LTC1861IS8#PBF LTC1861IS8#TRPBF LTC1861IS8#TRPBF
Versión de texto del documento
LTC1860/LTC1861
FuncTional block DiagraM
VCC CONV (SDI) SCK PIN NAMES IN PARENTHESES REFER TO LTC1861 CONVERT BIAS AND SERIAL SDO CLK SHUTDOWN PORT DATA IN 12-BITS IN+ (CH0) + 12-BIT SAMPLING DATA OUT IN– ADC – (CH1) 1860/61 BD GND VREF
TesT circuiTs Load Circuit for tdDO, tr, tf, tdis and ten Voltage Waveforms for SDO Rise and Fall Times, tr, tf
TEST POINT V SDO OH VOL 3k VCC tdis WAVEFORM 2, ten SDO tr tf 1860 TC04 tdis WAVEFORM 1 20pF 1860 TC01
Voltage Waveforms for ten Voltage Waveforms for tdis
CONV CONV VIH SDO 1860 TC03 SDO 90% WAVEFORM 1 ten (SEE NOTE 1) tdis
Voltage Waveforms for SDO Delay Times, tdDO and thDO
SDO WAVEFORM 2 10% (SEE NOTE 2) NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH SCK THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL VIL NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH tdDO THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL thDO 1860 TC05 VOH SDO VOL 1860 TC02 18601fb 10 For more information www.linear.com/LTC1860 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Typical Application Related Parts
FuncTional block DiagraM
VCC CONV (SDI) SCK PIN NAMES IN PARENTHESES REFER TO LTC1861 CONVERT BIAS AND SERIAL SDO CLK SHUTDOWN PORT DATA IN 12-BITS IN+ (CH0) + 12-BIT SAMPLING DATA OUT IN– ADC – (CH1) 1860/61 BD GND VREF
TesT circuiTs Load Circuit for tdDO, tr, tf, tdis and ten Voltage Waveforms for SDO Rise and Fall Times, tr, tf
TEST POINT V SDO OH VOL 3k VCC tdis WAVEFORM 2, ten SDO tr tf 1860 TC04 tdis WAVEFORM 1 20pF 1860 TC01
Voltage Waveforms for ten Voltage Waveforms for tdis
CONV CONV VIH SDO 1860 TC03 SDO 90% WAVEFORM 1 ten (SEE NOTE 1) tdis
Voltage Waveforms for SDO Delay Times, tdDO and thDO
SDO WAVEFORM 2 10% (SEE NOTE 2) NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH SCK THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL VIL NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH tdDO THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL thDO 1860 TC05 VOH SDO VOL 1860 TC02 18601fb 10 For more information www.linear.com/LTC1860 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Typical Application Related Parts