Datasheet LTC1852, LTC1853 (Analog Devices) - 10

LTC1852/LTC1853
APPLICATIONS INFORMATION
The LTC1852/LTC1853 are complete and very fl exible
DYNAMIC PERFORMANCE
data acquisition systems. They consist of a 10-bit/12-bit, 400ksps capacitive successive approximation A/D con-
Signal-to-(Noise + Distortion) Ratio
verter with a wideband sample-and-hold, a confi gurable The signal-to-noise plus distortion ratio [S/(N + D)] is the 8-channel analog input multiplexer, an internal reference ratio between the RMS amplitude of the fundamental input and reference buffer amplifi er, a 16-bit parallel digital frequency and the RMS amplitude of all other frequency output and digital control logic, including a programmable components at the ADC output. The output is band lim- sequencer. ited to frequencies above DC to below half the sampling frequency. The effective number of bits (ENOBs) is a
CONVERSION DETAILS
measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: The core analog-to-digital converter in the LTC1852/ LTC1853 uses a successive approximation algorithm and ENOB = [S/(N + D) – 1.76]/6.02 an internal sample-and-hold circuit to convert an analog where ENOB is the effective number of bits and S/(N + D) is signal to a 10-bit/12-bit parallel output. Conversion start expressed in dB. At the maximum sampling rate of 400kHz, is controlled by the CS and CONVST inputs. At the start the LTC1852/LTC1853 maintain near ideal ENOBs up to of the conversion, the successive approximation register and beyond the Nyquist input frequency of 200kHz. (SAR) is reset. Once a conversion cycle is begun, it cannot be restarted. During the conversion, the internal differen-
Total Harmonic Distortion
tial capacitive DAC output is sequenced by the SAR from the most signifi cant bit (MSB) to the least signifi cant bit Total harmonic distortion is the ratio of the RMS sum (LSB). The outputs of the analog input multiplexer are of all harmonics of the input signal to the fundamental connected to the sample-and-hold capacitors (C itself. The out-of-band harmonics alias into the frequency SAMPLE) during the acquire phase and the comparator offset is band between DC and half the sampling frequency. THD nulled by the zeroing switches. In this acquire phase, a is expressed as: minimum delay of 150ns will provide enough time for V22 + V32 + V42 +...Vn2 the sample-and-hold capacitors to acquire the analog THD = 20Log V1 signal. During the convert phase, the comparator zeroing switches are open, putting the comparator into compare where V1 is the RMS amplitude of the fundamental mode. The input switches connect CSAMPLE to ground, frequency and V2 through Vn are the amplitudes of the transferring the differential analog input charge onto the second through nth harmonics. The LTC1852/LTC1853 summing junction. This input charge is successively have good distortion performance up to the Nyquist compared with the binary weighted charges supplied by frequency and beyond. the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of the conversion,
Intermodulation Distortion
the differential DAC output balances the input charges. If the ADC input signal consists of more than one spectral The SAR contents (a 10-bit/12-bit data word), which component, the ADC transfer function nonlinearity can represents the difference of the analog input multiplexer produce intermodulation distortion (IMD) in addition to outputs, and the 4-bit address word are loaded into the THD. IMD is the change in one sinusoidal input caused 14-bit/16-bit output latches. by the presence of another sinusoidal input at a different frequency. 18523fa 10