Datasheet LTC1749 (Analog Devices)
| Fabricante | Analog Devices |
| Descripción | 12-Bit, 80Msps Wide Bandwidth ADC |
| Páginas / Página | 20 / 1 — FEATURES. DESCRIPTIO. Sample Rate: 80Msps. PGA Front End (2.25VP-P or … |
| Formato / tamaño de archivo | PDF / 289 Kb |
| Idioma del documento | Inglés |
FEATURES. DESCRIPTIO. Sample Rate: 80Msps. PGA Front End (2.25VP-P or 1.35VP-P Input Range). 71.8dB SNR and 87dB SFDR (PGA = 0)
Línea de modelo para esta hoja de datos
Versión de texto del documento
LTC1749 12-Bit, 80Msps Wide Bandwidth ADC
U FEATURES DESCRIPTIO
■
Sample Rate: 80Msps
The LTC®1749 is an 80Msps, 12-bit A/D converter de- ■
PGA Front End (2.25VP-P or 1.35VP-P Input Range)
signed for digitizing wide dynamic range signals up to ■
71.8dB SNR and 87dB SFDR (PGA = 0)
frequencies of 500MHz. The input range of the ADC can be ■
70.2dB SNR and 87dB SFDR (PGA = 1)
optimized with the on-chip PGA sample-and-hold circuit ■
500MHz Full Power Bandwidth S/H
and flexible reference circuitry. ■ No Missing Codes The LTC1749 has a highly linear sample-and-hold circuit ■ Single 5V Supply with a bandwidth of 500MHz. The SFDR is 80dB with an ■ Power Dissipation: 1.45W input frequency of 250MHz. Ultralow jitter of 0.15psRMS ■ Two Pin Selectable Reference Values allows undersampling of IF frequencies with minimal ■ Data Ready Output Clock degradation in SNR. DC specs include ±1LSB INL and no ■ Pin Compatible 14-Bit 80Msps Device (LTC1750) missing codes. ■ 48-Pin TSSOP Package The digital interface is compatible with 5V, 3V, 2V and
U
LVDS logic systems. The ENC and ENC inputs may be
APPLICATIO S
driven differentially from PECL, GTL and other low swing ■ Direct IF Sampling logic families or from single-ended TTL or CMOS. The low ■ Telecommunications noise, high gain ENC and ENC inputs may also be driven ■ Receivers by a sinusoidal signal without degrading performance. A ■ Cellular Base Stations separate output power supply can be operated from 0.5V ■ Spectrum Analysis to 5V, making it easy to connect directly to low voltage ■ Communications Test Equipment DSPs or FIFOs. ■ Undersampling The 48-pin TSSOP package with a flow-through pinout simplifies the board layout. , LTC and LT are registered trademarks of Linear Technology Corporation.
W BLOCK DIAGRA 80Msps, 12-Bit ADC with a 2.25V Differential Input Range
PGA OVDD 0.5V TO 5V 0.1µF 0.1µF A + IN ±1.125V CORRECTION 12 D11 S/H 12-BIT DIFFERENTIAL LOGIC AND OUTPUT • • – CIRCUIT PIPELINED ADC ANALOG INPUT A SHIFT LATCHES • IN D0 REGISTER CLKOUT SENSE OGND BUFFER VDD 5V RANGE 1µF 1µF 1µF SELECT DIFF AMP VCM GND 2VREF CONTROL LOGIC 4.7µF 1749 BD REFLB REFHA REFLA REFHB ENC ENC MSBINV 4.7µF 0.1µF 0.1µF DIFFERENTIAL 1µF 1µF ENCODE INPUT 1749f 1
U FEATURES DESCRIPTIO
■
Sample Rate: 80Msps
The LTC®1749 is an 80Msps, 12-bit A/D converter de- ■
PGA Front End (2.25VP-P or 1.35VP-P Input Range)
signed for digitizing wide dynamic range signals up to ■
71.8dB SNR and 87dB SFDR (PGA = 0)
frequencies of 500MHz. The input range of the ADC can be ■
70.2dB SNR and 87dB SFDR (PGA = 1)
optimized with the on-chip PGA sample-and-hold circuit ■
500MHz Full Power Bandwidth S/H
and flexible reference circuitry. ■ No Missing Codes The LTC1749 has a highly linear sample-and-hold circuit ■ Single 5V Supply with a bandwidth of 500MHz. The SFDR is 80dB with an ■ Power Dissipation: 1.45W input frequency of 250MHz. Ultralow jitter of 0.15psRMS ■ Two Pin Selectable Reference Values allows undersampling of IF frequencies with minimal ■ Data Ready Output Clock degradation in SNR. DC specs include ±1LSB INL and no ■ Pin Compatible 14-Bit 80Msps Device (LTC1750) missing codes. ■ 48-Pin TSSOP Package The digital interface is compatible with 5V, 3V, 2V and
U
LVDS logic systems. The ENC and ENC inputs may be
APPLICATIO S
driven differentially from PECL, GTL and other low swing ■ Direct IF Sampling logic families or from single-ended TTL or CMOS. The low ■ Telecommunications noise, high gain ENC and ENC inputs may also be driven ■ Receivers by a sinusoidal signal without degrading performance. A ■ Cellular Base Stations separate output power supply can be operated from 0.5V ■ Spectrum Analysis to 5V, making it easy to connect directly to low voltage ■ Communications Test Equipment DSPs or FIFOs. ■ Undersampling The 48-pin TSSOP package with a flow-through pinout simplifies the board layout. , LTC and LT are registered trademarks of Linear Technology Corporation.
W BLOCK DIAGRA 80Msps, 12-Bit ADC with a 2.25V Differential Input Range
PGA OVDD 0.5V TO 5V 0.1µF 0.1µF A + IN ±1.125V CORRECTION 12 D11 S/H 12-BIT DIFFERENTIAL LOGIC AND OUTPUT • • – CIRCUIT PIPELINED ADC ANALOG INPUT A SHIFT LATCHES • IN D0 REGISTER CLKOUT SENSE OGND BUFFER VDD 5V RANGE 1µF 1µF 1µF SELECT DIFF AMP VCM GND 2VREF CONTROL LOGIC 4.7µF 1749 BD REFLB REFHA REFLA REFHB ENC ENC MSBINV 4.7µF 0.1µF 0.1µF DIFFERENTIAL 1µF 1µF ENCODE INPUT 1749f 1