Datasheet LTC1609 (Analog Devices) - 7

LTC1609
U U U PIN FUNCTIONS (20-Pin SO/28-Pin SSOP) R1IN (Pin 1/Pin 1):
Analog Input. See Table 1 and Figure␣ 1 low, 16 clock pulses are output during each conversion. for input range connections. The pin will stay low between conversions.
AGND1 (Pin 2/Pin 2):
Analog Ground. Tie to analog ground
DATA (Pin 13/Pin 17):
Serial Data Output. The output data plane. is synchronized to the DATACLK and the format is deter- mined by SB/BTC. In the external shift clock mode, after 16
R2IN (Pin 3/Pin 3):
Analog Input. See Table 1 and Figure␣ 1 bits of data have been shifted out and CS is low and R/C is for input range connections. high, the level in the TAG pin will be outputted. This can be
R3IN (Pin 4/Pin 4):
Analog Input. See Table 1 and Figure␣ 1 used to daisy-chain the serial data output from several for input range connections. LTC1609s. If EXT/INT is low, the output data is valid on
NC (28-Pin SSOP Only—Pins 5, 8, 10, 11, 18, 20, 22,
both the rising and falling edge of the internal shift clock
23):
No Connect. which is outputted on DATACLK. In between conversions, DATA will stay at the level of the TAG input when the
CAP (Pin 5/Pin 6):
Reference Buffer Output. Bypass with conversion was started. 2.2µF tantalum capacitor.
TAG (Pin 14/Pin 19):
Tag input is used in the external clock
REF (Pin 6/Pin 7):
2.5V Reference Output. Bypass with mode. If EXT/INT is high, digital inputs applied to TAG will 2.2µF tantalum capacitor. Can be driven with an external be shifted out on DATA delayed 16 DATACLK pulses as reference. long as CS is low and R/C is high.
AGND2 (Pin 7/Pin 9):
Analog Ground. Tie to analog
R/C (Pin 15/Pin 21):
Read/Convert Input. With CS low, a ground plane. falling edge on R/C puts the internal sample-and-hold into
SB/BTC (Pin 8/Pin 12):
Select straight binary or two’s the hold state and starts a conversion. With CS low, a complement data output format. Tie pin high for straight rising edge on R/C enables the serial output data. binary or tie low for two’s complement format.
CS (Pin 16/Pin 24):
Chip Select. Internally OR’d with R/C.
EXT/INT (Pin 9/Pin 13):
Select external or internal clock With R/C low, a falling edge on CS will initiate a conversion. for shifting out the output data. Tie the pin high to With R/C high, a falling edge on CS will enable the serial synchronize the output data to the clock that is applied to output data. the DATACLK pin. If the pin is tied low, a convert command
BUSY (Pin 17/Pin 25):
Output Shows Converter Status. It will start transmitting the output data from the previous is low when a conversion is in progress. Data valid on the conversion synchronized to 16 clock pulses that are rising edge of BUSY. CS or R/C must be high when BUSY outputted on the DATACLK pin. rises or another conversion will start without time for
DGND (Pin 10/Pin 14):
Digital Ground. signal acquisition.
SYNC (Pin 11/Pin 15):
Sync Output. If EXT/INT is high,
PWRD (Pin 18/Pin 26):
Power Down Input. If the pin is tied either a rising edge on R/C with CS low or a falling edge on high, conversions are inhibited and power consumption is CS with R/C high will output a pulse on SYNC synchro- reduced (10µA typ). Results from the previous conversion nized to the external clock applied on the DATACLK pin. are maintained in the output shift register.
DATACLK (Pin 12/Pin 16):
Either an input or an output
VANA (Pin 19/Pin 27):
5V Analog Supply. Bypass to ground depending on the level set on EXT/INT. The output data is with a 0.1µF ceramic and a 10µF tantalum capacitor. synchronized to this clock. When EXT/INT is high an
VDIG (Pin 20/Pin 28):
5V Digital Supply. Connect directly external shift clock is applied to this pin. If EXT/INT is taken to VANA. 1609fa 7