Datasheet LTC1605-1, LTC1605-2 (Analog Devices) - 8

LTC1605-1/LTC1605-2
TesT circuiTs Load Circuit for Access Timing Load Circuit for Output Float Delay
5V 5V 1k 1k DBN DBN DBN DBN 1k CL CL 1k 50pF 50pF 1605-1/2 TC01 1605-1/2 TC02 A. HI-Z TO VOH AND VOL TO VOH B. HI-Z TO VOL AND VOH TO VOL A. VOH TO HI-Z B. VOL TO HI-Z
applicaTions inForMaTion Conversion Details
autozero switch, S3. In this acquire phase, a minimum delay of 2µs will provide enough time for the sample-and- The LTC1605-1/LTC1605-2 use a successive approxima- hold capacitor to acquire the analog signal. During the tion algorithm and an internal sample-and-hold circuit to convert phase, S3 opens, putting the comparator into the convert an analog signal to a 16-bit or two byte parallel compare mode. The input switch S2 switches CSAMPLE output. The ADC is complete with a precision reference and to ground, injecting the analog input charge onto the an internal clock. The control logic provides easy interface summing junction. This input charge is successively to microprocessors and DSPs. (Please refer to the Digital compared with the binary-weighted charges supplied by Interface section for the data format.) the capacitive DAC. Bit decisions are made by the high Conversion start is controlled by the CS and R/C inputs. speed comparator. At the end of a conversion, the DAC At the start of conversion, the successive approximation output balances the VIN input charge. The SAR contents register (SAR) is reset. Once a conversion cycle has begun, (a 16-bit data word) that represents the VIN are loaded it cannot be restarted. into the 16-bit output latches. During the conversion, the internal 16-bit capacitive DAC
Driving the Analog Inputs
output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to The nominal input range for the LTC1605-1 is 0V to 4V or Figure 1, VIN is connected through the resistor divider (1.6VREF) and for the LTC1605-2 the input range is ±4V and S1 to the sample-and-hold capacitor during the or (±1.6VREF). The inputs are overvoltage protected to acquire phase and the comparator offset is nulled by the ±25V. The input impedance is typically 10kΩ; therefore, it should be driven by a low impedance source. Wideband SAMPLE noise coupling into the input can be minimized by placing S1 C S3 SAMPLE a 1000pF capacitor at the input as shown in Figure 2. An RIN1 SAMPLE VIN – NPO-type capacitor gives the lowest distortion. Place the HOLD capacitor as close to the device input pin as possible. If RIN2 + an amplifier is to be used to drive the input, care should S2 CDAC COMPARATOR DAC be taken to select an amplifier with adequate accuracy, VDAC S linearity and noise for the application. The following list A is a summary of the op amps that are suitable for driving R the LTC1605-1/LTC1605-2. More detailed information 16-BIT is available in the Linear Technology data books and LATCH LinearViewTM CD-ROM. 1605-1/2 F01
Figure 1. LTC1605-1/LTC1605-2 Simplified Equivalent Circuit
LinearView is a trademark of Linear Technology Corporation 160512fa 8 For more information www.linear.com/LTC1605-1