Datasheet LTC1415 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | 12-Bit, 1.25Msps, 55mW Sampling A/D Converter |
| Páginas / Página | 24 / 7 — FU CTIO AL BLOCK DIAGRA. TEST CIRCUITS. Load Circuits for Access Timing. … |
| Formato / tamaño de archivo | PDF / 338 Kb |
| Idioma del documento | Inglés |
FU CTIO AL BLOCK DIAGRA. TEST CIRCUITS. Load Circuits for Access Timing. Load Circuits for Bus Relinquish Time
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LTC1415
U U W FU CTIO AL BLOCK DIAGRA
CSAMPLE +AIN AVDD CSAMPLE – AIN DVDD 2k ZEROING SWITCHES VREF 2.5V REF + REF AMP 12-BIT CAPACITIVE DAC COMP – REFCOMP (4.096V) OVDD AGND 12 SUCCESSIVE APPROXIMATION • D11 OUTPUT LATCHES • REGISTER • D0 DGND OGND INTERNAL CONTROL LOGIC CLOCK NAP/SLP SHDN CONVST RD CS BUSY 1415 BD
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Bus Relinquish Time
5V 5V 1k 1k DBN DBN DBN DBN 1k C 1k 100pF 100pF L CL (A) Hi-Z TO V (A) V OH AND VOL TO VOH (B) Hi-Z TO VOL AND VOH TO VOL OH TO Hi-Z (B) VOL TO Hi-Z 1415 TC01 1415 TC02 7
U U W FU CTIO AL BLOCK DIAGRA
CSAMPLE +AIN AVDD CSAMPLE – AIN DVDD 2k ZEROING SWITCHES VREF 2.5V REF + REF AMP 12-BIT CAPACITIVE DAC COMP – REFCOMP (4.096V) OVDD AGND 12 SUCCESSIVE APPROXIMATION • D11 OUTPUT LATCHES • REGISTER • D0 DGND OGND INTERNAL CONTROL LOGIC CLOCK NAP/SLP SHDN CONVST RD CS BUSY 1415 BD
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Bus Relinquish Time
5V 5V 1k 1k DBN DBN DBN DBN 1k C 1k 100pF 100pF L CL (A) Hi-Z TO V (A) V OH AND VOL TO VOH (B) Hi-Z TO VOL AND VOH TO VOL OH TO Hi-Z (B) VOL TO Hi-Z 1415 TC01 1415 TC02 7