Datasheet LTC1414 (Analog Devices) - 7

LTC1414
U U W U APPLICATIONS INFORMATION CONVERSION DETAILS
C + SAMPLE SAMPLE + The LTC1414 uses a successive approximation algorithm AIN HOLD ZEROING SWITCHES and an internal sample-and-hold circuit to convert an C – SAMPLE HOLD analog signal to a 14-bit parallel output. The ADC is SAMPLE A – IN complete with a precision reference and an internal clock. HOLD HOLD The device is easy to interface with microprocessors and C + DAC DSPs. (Please refer to the Digital Interface section for the + data format.) C – DAC COMP V + DAC – Conversion start is controlled by the CONVST input. At the start of the conversion the successive approximation V – 14 D13 register (SAR) is reset. Once a conversion cycle has begun DAC OUTPUT SAR LATCH D0 it cannot be restarted. 1414 F01 During the conversion, the internal differential 14-bit
Figure 1. Simplified Block Diagram
capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the A + –
Signal-to-Noise Ratio
IN and AIN inputs are connected to the sample-and-hold capacitors (CSAMPLE) The signal-to-(noise + distortion) ratio [S/(N + D)] is the during the acquire phase, and the comparator offset is ratio between the RMS amplitude of the fundamental input nulled by the zeroing switches. In this acquire phase, a frequency to the RMS amplitude of all other frequency minimum delay of 70ns will provide enough time for the components at the A/D output. The output is band limited sample-and-hold capacitors to acquire the analog signal. to frequencies from above DC and below half the sampling During the convert phase the comparator zeroing switches frequency. Figure 2a shows a typical spectral content with open, putting the comparator into compare mode. The a 2.2MHz sampling rate and a 100kHz input. The dynamic input switches connect the CSAMPLE capacitors to ground, performance is excellent for input frequencies up to and transferring the differential analog input charge onto the beyond the Nyquist limit of 1.1MHz. (See Figure 2b) summing junction. This input charge is successively com- pared with the binary-weighted charges supplied by the 0 differential capacitive DAC. Bit decisions are made by the SINAD = 80dB SFDR = 96dB high speed comparator. At the end of a conversion, the –20 fSAMPLE = 2.2MHz differential DAC output balances the A + – IN and AIN input f –40 IN = 97.753kHz charges. The SAR contents (a 14-bit data word) which represents the difference of A + – –60 IN and AIN are loaded into the 14-bit output latches. AMPLITUDE (dB) –80
DYNAMIC PERFORMANCE
–100 The LTC1414 has excellent high speed sampling capabil- –120 0 200 400 600 800 1000 ity. FFT (Fast Four Transform) test techniques are used to FREQUENCY (kHz) test the ADC’s frequency response, distortion and noise at 1414 F02a the rated throughput. By applying a low distortion sine
Figure 2a. LTC1414 Nonaveraged, 2048 Point FFT,
wave and analyzing the digital output using an FFT algo-
Input Frequency = 100kHz
rithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figure 2 shows a typical LTC1414 FFT plot. 7