Datasheet LTC1408-12 (Analog Devices) - 4

LTC1408-12
W U POWER REQUIRE E TS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. With internal reference, VDD = VCC= 3V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD, VCC Supply Voltage 2.7 3.0 3.6 V IDD + ICC Supply Current Active Mode, fSAMPLE = 600ksps ● 5 7 mA Nap Mode ● 1.1 1.9 mA Sleep Mode 2.0 15 µA PD Power Dissipation Active Mode with SCK, fSAMPLE = 600ksps 15 mW
W U TI I G CHARACTERISTICS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. VDD = 3V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Rate per Channel ● 100 kHz (Conversion Rate) tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisiton Period) ● 10 µs tSCK Clock Period (Note 16) ● 100 10000 ns tCONV Conversion Time (Notes 6, 17) 96 SCLK cycles t1 Minimum High or Low SCLK Pulse Width (Note 6) 2 ns t2 CONV to SCK Setup Time (Notes 6, 10) 3 10000 ns t3 SCK Before CONV (Note 6) 0 ns t4 Minimum High or Low CONV Pulse Width (Note 6) 4 ns t5 SCK↑ to Sample Mode (Note 6) 4 ns t6 CONV↑ to Hold Mode (Notes 6, 11) 1.2 ns t7 96th SCK↑ to CONV↑ Interval (Affects Acquisition Period) (Notes 6, 7, 13) 45 ns t8 Delay from SCK to Valid Bits 0 Through 11 (Notes 6, 12) 8 ns t9 SCK↑ to Hi-Z at SDO (Notes 6, 12) 6 ns t10 Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns t11 VREF Settling Time After Sleep-to-Wake Transition (Notes 6, 14) 2 ms
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 9:
The absolute voltage at CHx+ and CHx– must be within this range. may cause permanent damage to the device. Exposure to any Absolute
Note 10:
If less than 3ns is allowed, the output data will appear one clock Maximum Rating condition for extended periods may affect device cycle later. It is best for CONV to rise half a clock before SCK, when reliabilty and lifetime. running the clock at rated speed.
Note 2:
All voltage values are with respect to ground GND.
Note 11:
Not the same as aperture delay. Aperture delay (1ns) is the
Note 3:
When these pins are taken below GND or above VDD, they will be difference between the 2.2ns delay through the sample-and-hold and the clamped by internal diodes. This product can handle input currents greater 1.2ns CONV to Hold mode delay. than 100mA below GND or greater than VDD without latchup.
Note 12:
The rising edge of SCK is guaranteed to catch the data coming
Note 4:
Offset and range specifications apply for a single-ended CH0+ – out into a storage latch. CH5+ input with CH0– – CH5– grounded and using the internal 2.5V
Note 13:
The time period for acquiring the input signal is started by the reference. 96th rising clock and it is ended by the rising edge of CONV.
Note 5:
Integral linearity is tested with an external 2.55V reference and is
Note 14:
The internal reference settles in 2ms after it wakes up from Sleep defined as the deviation of a code from the straight line passing through mode with one or more cycles at SCK and a 10µF capacitive load. the actual endpoints of a transfer curve. The deviation is measured from
Note 15:
The full power bandwidth is the frequency where the output code the center of quantization band. Linearity is tested for CH0 only. swing drops by 3dB with a 2.5VP-P input sine wave.
Note 6:
Guaranteed by design, not subject to test.
Note 16:
Maximum clock period guarantees analog performance during
Note 7:
Recommended operating conditions. conversion. Output data can be read with an arbitrarily long clock period.
Note 8:
The analog input range is defined for the voltage difference
Note 17:
The conversion process takes 16 clocks for each channel that is between CHx+ and CHx–, x = 0–5. enabled, up to 96 clocks for all 6 channels. 140812f 4