Datasheet LTC1408 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | 6 Channel, 14-Bit, 600ksps Simultaneous Sampling ADC with Shutdown |
| Páginas / Página | 20 / 7 — TYPICAL PERFOR A CE CHARACTERIST. ICS DD = 3V, TA = 25. Simultaneous Step … |
| Formato / tamaño de archivo | PDF / 513 Kb |
| Idioma del documento | Inglés |
TYPICAL PERFOR A CE CHARACTERIST. ICS DD = 3V, TA = 25. Simultaneous Step at all 6 Channels from 25
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LTC1408
W U TYPICAL PERFOR A CE CHARACTERIST V ICS DD = 3V, TA = 25
°
C Simultaneous Step at all 6 Channels from 25
Ω
Source Sampling Frequency = 625ksps Input Frequency = 625.0381MHz PSRR vs Frequency
16384 0 14336 CH0 THRU CH5 –20 12288 RISING 10240 –40 8192 –60 OUTPUT CODE 6144 CMRR (dB) –80 4096 CH0 THRU CH5 2048 FALLING –100 0–5 0 5 –120 10 15 20 25 100 1k 10k 100k 1M 10M 100M 1G TIME (ns) FREQUENCY (Hz) 1408 G22 1408 G23
U U U PI FU CTIO S SDO (Pin 1):
Three-State Serial Data Output. Each set of
GND (Pins 6, 9, 12, 13, 16, 19):
Analog Grounds. These six output data words represent the six analog input ground pins must be tied directly to the solid ground plane channels at the start of the previous conversion. Data for under the part. Analog signal currents flow through these CH0 comes out first and data for CH5 comes out last. Each connections. data word comes out MSB first.
CH1+ (Pin 7):
Non-Inverting Channel 1. CH1+ operates
OGND (Pin 2):
Ground Return for SDO Currents. This pad fully differentially with respect to CH1– with a 0V to 2.5V, must always be within 300mV of the ground plane poten- or ±1.25V differential swing and a 0V to VDD absolute tial. input range.
OVDD (Pin 3):
Power Supply for the SDO Pin. OVDD must
CH1– (Pin 8):
Inverting Channel 1. CH1– operates fully be no more than 300mV higher than VDD and can be differentially with respect to CH1+ with a –2.5V to 0V, brought to a lower voltage to interface to low voltage logic or ±1.25V differential swing and a 0V to VDD absolute families. The unloaded high state at SDO is at the potential input range. of OVDD.
CH2+ (Pin 10):
Non-Inverting Channel 2. CH2+ operates
CH0+ (Pin 4):
Non-Inverting Channel 0. CH0+ operates fully differentially with respect to CH2– with a 0V to 2.5V, fully differentially with respect to CH0– with a 0V to 2.5V, or ±1.25V differential swing and a 0V to VDD absolute or ±1.25V differential swing and a 0V to VDD absolute input range. input range.
CH2– (Pin 11):
Inverting Channel 2. CH2– operates fully
CH0– (Pin 5):
Inverting Channel 0. CH0– operates fully differentially with respect to CH2+ with a –2.5V to 0V, or differentially with respect to CH0+ with a –2.5V to 0V, ±1.25V differential swing and a 0V to VDD absolute or ±1.25V differential swing and a 0V to VDD absolute input range. input range. 1408fa 7
W U TYPICAL PERFOR A CE CHARACTERIST V ICS DD = 3V, TA = 25
°
C Simultaneous Step at all 6 Channels from 25
Ω
Source Sampling Frequency = 625ksps Input Frequency = 625.0381MHz PSRR vs Frequency
16384 0 14336 CH0 THRU CH5 –20 12288 RISING 10240 –40 8192 –60 OUTPUT CODE 6144 CMRR (dB) –80 4096 CH0 THRU CH5 2048 FALLING –100 0–5 0 5 –120 10 15 20 25 100 1k 10k 100k 1M 10M 100M 1G TIME (ns) FREQUENCY (Hz) 1408 G22 1408 G23
U U U PI FU CTIO S SDO (Pin 1):
Three-State Serial Data Output. Each set of
GND (Pins 6, 9, 12, 13, 16, 19):
Analog Grounds. These six output data words represent the six analog input ground pins must be tied directly to the solid ground plane channels at the start of the previous conversion. Data for under the part. Analog signal currents flow through these CH0 comes out first and data for CH5 comes out last. Each connections. data word comes out MSB first.
CH1+ (Pin 7):
Non-Inverting Channel 1. CH1+ operates
OGND (Pin 2):
Ground Return for SDO Currents. This pad fully differentially with respect to CH1– with a 0V to 2.5V, must always be within 300mV of the ground plane poten- or ±1.25V differential swing and a 0V to VDD absolute tial. input range.
OVDD (Pin 3):
Power Supply for the SDO Pin. OVDD must
CH1– (Pin 8):
Inverting Channel 1. CH1– operates fully be no more than 300mV higher than VDD and can be differentially with respect to CH1+ with a –2.5V to 0V, brought to a lower voltage to interface to low voltage logic or ±1.25V differential swing and a 0V to VDD absolute families. The unloaded high state at SDO is at the potential input range. of OVDD.
CH2+ (Pin 10):
Non-Inverting Channel 2. CH2+ operates
CH0+ (Pin 4):
Non-Inverting Channel 0. CH0+ operates fully differentially with respect to CH2– with a 0V to 2.5V, fully differentially with respect to CH0– with a 0V to 2.5V, or ±1.25V differential swing and a 0V to VDD absolute or ±1.25V differential swing and a 0V to VDD absolute input range. input range.
CH2– (Pin 11):
Inverting Channel 2. CH2– operates fully
CH0– (Pin 5):
Inverting Channel 0. CH0– operates fully differentially with respect to CH2+ with a –2.5V to 0V, or differentially with respect to CH0+ with a –2.5V to 0V, ±1.25V differential swing and a 0V to VDD absolute or ±1.25V differential swing and a 0V to VDD absolute input range. input range. 1408fa 7