Datasheet LTC1403, LTC1403A (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | Serial 14-Bit, 2.8Msps Sampling ADCs with Shutdown |
| Páginas / Página | 22 / 8 — pin Functions. A +. IN (Pin 1):. A –. IN (Pin 2):. SDO (Pin 8):. REF (Pin … |
| Formato / tamaño de archivo | PDF / 370 Kb |
| Idioma del documento | Inglés |
pin Functions. A +. IN (Pin 1):. A –. IN (Pin 2):. SDO (Pin 8):. REF (Pin 3):. SCK (Pin 9):. GND (Pins 5, 6, 11):. CONV (Pin 10):
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LTC1403/LTC1403A
pin Functions A +
+
IN (Pin 1):
Noninverting Analog Input. AIN operates solid analog ground plane with a 10µF ceramic capacitor fully differentially with respect to A – IN with a 0V to 2.5V (or 10µF tantalum in parallel with 0.1µF ceramic). Keep in differential swing and a 0V to VDD common mode swing. mind that internal analog currents and digital output signal
A –
– currents flow through this pin. Care should be taken to
IN (Pin 2):
Inverting Analog Input. AIN operates fully differentially with respect to A + place the 0.1µF bypass capacitor as close to Pins 6 and IN with a –2.5V to 0V differential swing and a 0V to V 7 as possible. DD common mode swing.
V SDO (Pin 8):
Three-State Serial Data Output. Each of output
REF (Pin 3):
2.5V Internal Reference. Bypass to GND + and to a solid analog ground plane with a 10µF ceramic data words represents the difference between AIN and – capacitor (or 10µF tantalum in parallel with 0.1µF ceramic). AIN analog inputs at the start of the previous conversion. Can be overdriven by an external reference between 2.55V
SCK (Pin 9):
External Clock Input. Advances the conver- and VDD. sion process and sequences the output data on the rising
GND (Pins 5, 6, 11):
Ground and Exposed Pad. These edge. Responds to TTL (≤3V) and 3V CMOS levels. One ground pins and the exposed pad must be tied directly to or more pulses wake from sleep. the solid ground plane under the part. Keep in mind that
CONV (Pin 10):
Convert Start. Holds the analog input signal analog signal currents and digital output signal currents and starts the conversion on the rising edge. Responds flow through these pins. to TTL (≤3V) and 3V CMOS levels. Two pulses with SCK
V
in fixed high or fixed low state start Nap mode. Four or
DD (Pin 7):
3V Positive Supply. This single power pin supplies 3V to the entire chip. Bypass to GND and to a more pulses with SCK in fixed high or fixed low state start Sleep mode.
Block Diagram
10µF 3V 7 LTC1403A VDD A + IN 1 + THREE- TCH STATE S & H 14-BIT ADC SERIAL 8 SDO A – OUTPUT IN 2 – 14-BIT LA PORT 14 VREF 3 10 CONV 10µF 2.5V TIMING REFERENCE LOGIC GND 4 9 SCK 1403A BD 5 6 11 EXPOSED PAD 1403fc 8 For more information www.linear.com/LTC1403 Document Outline Features Applications Block Diagram Description Absolute Maximum Ratings Order Information Pin Configuration Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Applications Information Package Description Revision History Related Parts
pin Functions A +
+
IN (Pin 1):
Noninverting Analog Input. AIN operates solid analog ground plane with a 10µF ceramic capacitor fully differentially with respect to A – IN with a 0V to 2.5V (or 10µF tantalum in parallel with 0.1µF ceramic). Keep in differential swing and a 0V to VDD common mode swing. mind that internal analog currents and digital output signal
A –
– currents flow through this pin. Care should be taken to
IN (Pin 2):
Inverting Analog Input. AIN operates fully differentially with respect to A + place the 0.1µF bypass capacitor as close to Pins 6 and IN with a –2.5V to 0V differential swing and a 0V to V 7 as possible. DD common mode swing.
V SDO (Pin 8):
Three-State Serial Data Output. Each of output
REF (Pin 3):
2.5V Internal Reference. Bypass to GND + and to a solid analog ground plane with a 10µF ceramic data words represents the difference between AIN and – capacitor (or 10µF tantalum in parallel with 0.1µF ceramic). AIN analog inputs at the start of the previous conversion. Can be overdriven by an external reference between 2.55V
SCK (Pin 9):
External Clock Input. Advances the conver- and VDD. sion process and sequences the output data on the rising
GND (Pins 5, 6, 11):
Ground and Exposed Pad. These edge. Responds to TTL (≤3V) and 3V CMOS levels. One ground pins and the exposed pad must be tied directly to or more pulses wake from sleep. the solid ground plane under the part. Keep in mind that
CONV (Pin 10):
Convert Start. Holds the analog input signal analog signal currents and digital output signal currents and starts the conversion on the rising edge. Responds flow through these pins. to TTL (≤3V) and 3V CMOS levels. Two pulses with SCK
V
in fixed high or fixed low state start Nap mode. Four or
DD (Pin 7):
3V Positive Supply. This single power pin supplies 3V to the entire chip. Bypass to GND and to a more pulses with SCK in fixed high or fixed low state start Sleep mode.
Block Diagram
10µF 3V 7 LTC1403A VDD A + IN 1 + THREE- TCH STATE S & H 14-BIT ADC SERIAL 8 SDO A – OUTPUT IN 2 – 14-BIT LA PORT 14 VREF 3 10 CONV 10µF 2.5V TIMING REFERENCE LOGIC GND 4 9 SCK 1403A BD 5 6 11 EXPOSED PAD 1403fc 8 For more information www.linear.com/LTC1403 Document Outline Features Applications Block Diagram Description Absolute Maximum Ratings Order Information Pin Configuration Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Applications Information Package Description Revision History Related Parts