Datasheet LTC1403, LTC1403A (Analog Devices) - 5

LTC1403/LTC1403A
timing characteristics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency per Channel (Conversion Rate) l 2.8 MHz tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisition Period) l 357 ns tSCK Clock Period (Notes 16) l 19.8 10000 ns tCONV Conversion Time (Note 6) 17 18 SCLK cycles t1 Minimum Positive or Negative SCLK Pulse Width (Note 6) 2 ns t2 CONV to SCK Setup Time (Notes 6, 10) 3 ns t3 Nearest SCK Edge Before CONV (Note 6) 0 ns t4 Minimum Positive or Negative CONV Pulse Width (Note 6) 4 ns t5 SCK to Sample Mode (Note 6) 4 ns t6 CONV to Hold Mode (Notes 6, 11) 1.2 ns t7 16th SCK↑ to CONV↑ Interval (Affects Acquisition Period) (Notes 6, 7, 13) 45 ns t8 Minimum Delay from SCK to Valid Bits 0 Through 13 (Notes 6, 12) 8 ns t9 SCK to Hi-Z at SDO (Notes 6, 12) 6 ns t10 Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns t12 VREF Settling Time After Sleep-to-Wake Transition (Notes 6, 14) 2 ms
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 10:
If less than 3ns is allowed, the output data will appear one may cause permanent damage to the device. Exposure to any Absolute clock cycle later. It is best for CONV to rise half a clock before SCK, when Maximum Rating condition for extended periods may affect device running the clock at rated speed. reliability and lifetime.
Note 11:
Not the same as aperture delay. Aperture delay is smaller (1ns)
Note 2:
All voltage values are with respect to GND. because the 2.2ns delay through the sample-and-hold is subtracted from
Note 3:
When these pins are taken below GND or above V the CONV to Hold mode delay. DD, they will be clamped by internal diodes. This product can handle input currents greater
Note 12:
The rising edge of SCK is guaranteed to catch the data coming than 100mA below GND or greater than VDD without latchup. out into a storage latch.
Note 4:
Offset and full-scale specifications are measured for a single-
Note 13:
The time period for acquiring the input signal is started by the ended A + – IN input with AIN grounded and using the internal 2.5V reference. 16th rising clock and it is ended by the rising edge of convert.
Note 5:
Integral linearity is tested with an external 2.55V reference and is
Note 14:
The internal reference settles in 2ms after it wakes up from Sleep defined as the deviation of a code from the straight line passing through mode with one or more cycles at SCK and a 10µF capacitive load. the actual endpoints of a transfer curve. The deviation is measured from
Note 15:
The full power bandwidth is the frequency where the output code the center of quantization band. swing drops to 3dB with a 2.5VP-P input sine wave.
Note 6:
Guaranteed by design, not subject to test.
Note 16:
Maximum clock period guarantees analog performance during
Note 7:
Recommended operating conditions. conversion. Output data can be read without an arbitrarily long clock.
Note 8:
The analog input range is defined for the voltage difference
Note 17:
VDD = 3V, fSAMPLE = 2.8Msps. between A + – IN and AIN .
Note 18:
The LTC1403A is measured and specified with 14-bit Resolution
Note 9:
The absolute voltage at A + – IN and AIN must be within this range. (1LSB = 152µV) and the LTC1403 is measured and specified with 12-bit Resolution (1LSB = 610µV). 1403fc For more information www.linear.com/LTC1403 5 Document Outline Features Applications Block Diagram Description Absolute Maximum Ratings Order Information Pin Configuration Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Applications Information Package Description Revision History Related Parts