Datasheet LTC1401 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | Complete SO-8, 12-Bit, 200ksps ADC with Shutdown |
| Páginas / Página | 20 / 6 — PIN FUNCTIONS VCC (Pin 1):. CLK (Pin 6):. AIN (Pin 2):. CONV (Pin 7):. … |
| Formato / tamaño de archivo | PDF / 254 Kb |
| Idioma del documento | Inglés |
PIN FUNCTIONS VCC (Pin 1):. CLK (Pin 6):. AIN (Pin 2):. CONV (Pin 7):. VREF (Pin 3):. GND (Pin 4):. SHDN (Pin 8):. DOUT (Pin 5):
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LTC1401
U U U PIN FUNCTIONS VCC (Pin 1):
Positive Supply, 3V. Bypass to GND (10µF
CLK (Pin 6):
Clock. This clock synchronizes the serial data tantalum in parallel with 0.1µF ceramic). transfer. A minimum CLK pulse of 60ns signals the ADC to wake up from Nap or Sleep mode.
AIN (Pin 2):
Analog Input. 0V to 2.048V.
CONV (Pin 7):
Conversion Start Signal. This active high
VREF (Pin 3):
1.2V Reference Output. Bypass to GND signal starts a conversion on its rising edge. Keeping CLK (10µF tantalum in parallel with 0.1µF ceramic). low and pulsing CONV two/four times will put the ADC into
GND (Pin 4):
Ground. GND should be tied directly to an Nap/Sleep mode. analog ground plane.
SHDN (Pin 8):
Shutdown Input. Pull this pin Low to put the
DOUT (Pin 5):
The A/D conversion result is shifted out from ADC in Shutdown mode and save power (REFRDY will go this pin. Low). The device will draw 4.5µA in this mode.
U U W FUNCTIONAL BLOCK DIAGRA
C ZEROING SWITCH SAMPLE A V IN CC GND SHDN VREF 1.20V REF 12-BIT CAPACITIVE DAC COMP CLK CONTROL 12 LOGIC CONV SUCCESSIVE APPROXIMATION REGISTER/PARALLEL TO DOUT SERIAL CONVERTER LTC1401 • BD01
TEST CIRCUITS
3V 3k DOUT DOUT 3k CLOAD CLOAD Hi-Z TO VOH Hi-Z TO VOL VOL TO VOH VOH TO VOL VOH TO Hi-Z VOL TO Hi-Z LTC1401 • TC01 1401fa 6
U U U PIN FUNCTIONS VCC (Pin 1):
Positive Supply, 3V. Bypass to GND (10µF
CLK (Pin 6):
Clock. This clock synchronizes the serial data tantalum in parallel with 0.1µF ceramic). transfer. A minimum CLK pulse of 60ns signals the ADC to wake up from Nap or Sleep mode.
AIN (Pin 2):
Analog Input. 0V to 2.048V.
CONV (Pin 7):
Conversion Start Signal. This active high
VREF (Pin 3):
1.2V Reference Output. Bypass to GND signal starts a conversion on its rising edge. Keeping CLK (10µF tantalum in parallel with 0.1µF ceramic). low and pulsing CONV two/four times will put the ADC into
GND (Pin 4):
Ground. GND should be tied directly to an Nap/Sleep mode. analog ground plane.
SHDN (Pin 8):
Shutdown Input. Pull this pin Low to put the
DOUT (Pin 5):
The A/D conversion result is shifted out from ADC in Shutdown mode and save power (REFRDY will go this pin. Low). The device will draw 4.5µA in this mode.
U U W FUNCTIONAL BLOCK DIAGRA
C ZEROING SWITCH SAMPLE A V IN CC GND SHDN VREF 1.20V REF 12-BIT CAPACITIVE DAC COMP CLK CONTROL 12 LOGIC CONV SUCCESSIVE APPROXIMATION REGISTER/PARALLEL TO DOUT SERIAL CONVERTER LTC1401 • BD01
TEST CIRCUITS
3V 3k DOUT DOUT 3k CLOAD CLOAD Hi-Z TO VOH Hi-Z TO VOL VOL TO VOH VOH TO VOL VOH TO Hi-Z VOL TO Hi-Z LTC1401 • TC01 1401fa 6