Datasheet LTC1291 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | Single Chip 12-Bit Data Acquisition System |
| Páginas / Página | 20 / 7 — TEST CIRCUITS. Voltage Waveforms for DOUT Rise and Fall Times, tr, tf. … |
| Formato / tamaño de archivo | PDF / 342 Kb |
| Idioma del documento | Inglés |
TEST CIRCUITS. Voltage Waveforms for DOUT Rise and Fall Times, tr, tf. Voltage Waveforms for DOUT Delay Time, tdDO
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LTC1291
TEST CIRCUITS Voltage Waveforms for DOUT Rise and Fall Times, tr, tf Voltage Waveforms for DOUT Delay Time, tdDO
CLK 2.4V 0.8V DOUT 0.4V tdDO 2.4V tr tf 1291 TC04 DOUT 0.4V 1291 TC03
Voltage Waveforms for ten
CS DIN START CLK 1 2 3 4 5 DOUT 0.8V B11 ten 1291 TC07
O U U W U APPLICATI S I FOR ATIO
The LTC1291 is a data acquisition component which being transmitted on the falling CLK edge and captured on contains the following functional blocks: the rising CLK edge in both transmitting and receiving 1. 12-bit successive approximation capacitive A/D systems. converter 2. Analog multiplexer (MUX) CS 3. Sample-and-hold (S/H) DIN 1 DIN 2 4. Synchronous, half duplex serial interface DOUT 1 DOUT 2 5. Control and timing logic SHIFT MUX 1 NULL SHIFT A/D CONVERSION ADDRESS IN BIT RESULT OUT 1291 F01
DIGITAL CONSIDERATIONS Figure 1 Serial Interface
The LTC1291 communicates with microprocessors and The input data is first received and then the A/D conversion other external circuitry via a synchronous, half duplex, result is transmitted (half duplex). Because of the half 4-wire serial interface (see Operating Sequence). The duplex operation DIN and DOUT may be tied together clock (CLK) synchronizes the data transfer with each bit allowing transmission over just 3 wires: CS, CLK and 1291fa 7
TEST CIRCUITS Voltage Waveforms for DOUT Rise and Fall Times, tr, tf Voltage Waveforms for DOUT Delay Time, tdDO
CLK 2.4V 0.8V DOUT 0.4V tdDO 2.4V tr tf 1291 TC04 DOUT 0.4V 1291 TC03
Voltage Waveforms for ten
CS DIN START CLK 1 2 3 4 5 DOUT 0.8V B11 ten 1291 TC07
O U U W U APPLICATI S I FOR ATIO
The LTC1291 is a data acquisition component which being transmitted on the falling CLK edge and captured on contains the following functional blocks: the rising CLK edge in both transmitting and receiving 1. 12-bit successive approximation capacitive A/D systems. converter 2. Analog multiplexer (MUX) CS 3. Sample-and-hold (S/H) DIN 1 DIN 2 4. Synchronous, half duplex serial interface DOUT 1 DOUT 2 5. Control and timing logic SHIFT MUX 1 NULL SHIFT A/D CONVERSION ADDRESS IN BIT RESULT OUT 1291 F01
DIGITAL CONSIDERATIONS Figure 1 Serial Interface
The LTC1291 communicates with microprocessors and The input data is first received and then the A/D conversion other external circuitry via a synchronous, half duplex, result is transmitted (half duplex). Because of the half 4-wire serial interface (see Operating Sequence). The duplex operation DIN and DOUT may be tied together clock (CLK) synchronizes the data transfer with each bit allowing transmission over just 3 wires: CS, CLK and 1291fa 7